Principal Layout Design Engineer

Custom layout design for analog and digital blocks using 3nm technology.

About the role

As a key member of the layout team, you will be responsible for delivering clean layouts that meet LVS, DRC, ERC, EM, and IR requirements. You will collaborate closely with engineering teams to ensure full-chip integration and custom macro implementation using 3nm technology.

What you'll do

• Design complex layouts for both analog and digital circuits using deep submicron technologies.
• Collaborate with Place & Route (P&R) teams to resolve full-chip integration issues and integrate custom macros.
• Floorplan and build out cells, blocks, and macros, including creating and debugging LEF files.
• Analyze and interpret LVS, DRC, ERC, EM, and IR results to isolate and resolve physical verification issues.
• Support and assist layout delivery during tapeout phases across multiple projects and technologies.
• Coach and train junior engineers to develop layout skills within the team.

What you'll need

• Bachelor's degree with 8 years of related experience, Master's degree with 6 years, or PhD with 3 years.
• Minimum of 8 years of experience in custom layout design.
• Hands-on experience with 3nm technology.
• High proficiency in laying out custom digital components such as SRAM, register files, and standard cells.
• Strong skills designing custom analog blocks, including amplifiers and resistor ladders.
• Expertise in laying out and balancing custom clock H-trees for full-chip designs.
• Solid knowledge of Design for Manufacturability (DFM), hierarchical layout techniques, device matching, and low-parasitic layout practices.
• Proficiency with Cadence XL/GXL/EXL and Mentor Graphics Calibre verification tools.
• Understanding of Electromigration (EM) and IR drop analysis.

Nice to have

• Familiarity with Cadence Innovus.
• Experience with Totem tools for EM/IR analysis.
• Programming skills.

Skills: custom layout, 3nm, LVS, DRC, Virtuoso, Calibre

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