Technical Staff Engineer - Design Implementation - AZ - Chandler, United States
Originally posted 23 June 2026 by the employer.
Join Microchip Technology to drive implementation flows and timing closure for 12nm silicon and multi-die integration.
About the role
This role focuses on methodology development and implementation flows for 12nm silicon, centering on hierarchical SoC execution, timing convergence, and multi-die design enablement. You will shape scalable RTL-to-silicon methodologies and establish implementation practices across complex SoC programs.
What you'll do
- Develop and deploy SoC implementation flows involving hierarchical design planning, logic synthesis, timing closure, power analysis, and low-power implementation methodologies using UPF specification. - Define top-level timing methodologies across IPs, subsystems, and full-chip integration to ensure convergence to signoff targets. - Drive design implementation methodology for multi-die integration, timing constraints strategy, and integration flows. - Influence design partitioning decisions by evaluating impact on implementation complexity, timing closure, power, yield, and scalability. - Develop timing constraints for complex blocks and SoCs, including clock definition, exception strategy, and interface budgeting. - Partner with the physical design team to drive floorplanning decisions and clock tree constraints, and mentor engineers on implementation flows and multi-die design best practices.
What you'll need
- BS or MS in Electrical Engineering or a related field with 14+ years of experience in SoC implementation activities. - Hands-on expertise in synthesis, UPF specification, timing closure, hierarchical implementation, and low-power digital design flows. - Hands-on experience with industry standard EDA tools: Genus, iSpatial, Design Compiler, Fusion Compiler, Tempus, PrimeTime, PrimePower, VCLP, RTL Architect, Conformal, or Formality. - Deep understanding of SoC timing architecture, including clocking strategy, constraint development, timing budgeting, and block-to-top convergence. - Ability to incorporate system-level timing specifications into implementation constraints for synthesis and timing closure. - Background in digital microarchitecture, RTL coding, and front-end to implementation handoff quality, with experience establishing flows in first-generation product environments.
Skills: SoC implementation flows, hierarchical design planning, timing closure, multi-die integration, UPF specification
This role has been open 121 days — well above the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Microchip Technology | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 14 | 664 |
| Open roles in the wider Physical Implementation family | 28 | 1489 · 110 employers |
| Median days open | 75 d | 62 d (+13 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SoC implementation flows, hierarchical design planning, timing closure, multi-die integration, UPF specification
Who's hiring in this category
- Qualcomm · 119 open roles · median 45 d
- AMD · 61 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 67 d
- Synopsys · 38 open roles · median 36 d
- Broadcom · 35 open roles · median 101 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.