Technical Segment Product Manager - Memory Test Division
$174,700 - $279,500 USD yearly
Originally posted 2 November 2026 by the employer.
About the role
As a Technical Segment Product Manager in the Memory Test Division, you will independently own a major market segment, product portfolio, or strategic technology area across product lifecycle decisions, design-ins, go-to-market execution, and financial performance.
What you'll do
- Lead technical design-in activities by guiding market analysis, identifying priority targets, and partnering with Sales on account strategy, technical collateral, and commercial agreements.
- Own the full product lifecycle for assigned products, managing positioning, pricing recommendations, licensing, forecasting, launch, sustainment, end-of-production, and last-time-buy strategy.
- Lead technical marketing and go-to-market execution, including competitive analysis, sales tools, technical marketing collateral, and launch readiness.
- Manage segment financial planning across revenue, margin, R&D, applications investment, inventory assumptions, and long-term forecasts supporting LTB, E&O, and EOL decisions.
- Lead mid-term market segment strategy across a five-year horizon and establish annual plans with revenue, contribution margin, market-share, and design-in targets.
- Lead customer product presentations and roadmap discussions detailing solution capabilities, differentiation, and technical fit with customer requirements.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related technical field.
- Typically 8–12+ years of experience in product marketing, product management, applications engineering, product engineering, test engineering, or related semiconductor roles.
- Deep understanding of semiconductor memory products, customer requirements, market dynamics, and competitive positioning.
- Experience with pricing, revenue and margin planning, investment trade-offs, and long-range forecasting.
- Demonstrated background leading complex product, design-in, lifecycle, or go-to-market initiatives in a matrixed global organization.
- Ability to complete domestic and international travel of approximately 15–20%.
Nice to have
- Advanced degree (MS or MBA).
- Experience with memory ATE, test solutions, or complex semiconductor systems.
More semiconductor jobs: Teradyne jobs · Test engineer jobs · San Jose jobs
This role has been open 0 days — well below the 39-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
609
|
Median days open
39 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Teradyne | All employers we track in this specialty (609 roles · 81 employers) |
|---|---|---|
| Open roles in this specialty | 87 | 609 |
| Open roles in the wider Silicon Validation & Test family | 102 | 2323 · 111 employers |
| Median days open | 32 d | 39 d (−7 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne (this employer) · 86 open roles · median 32 d
- Renesas Electronics · 47 open roles · median 31 d
- Infineon Technologies · 45 open roles · median 38 d
- Qualcomm · 29 open roles · median 45 d
- Micron Technology · 28 open roles · median 49 d
- Texas Instruments · 28 open roles · median 40 d
How we counted: 609 open Silicon Test Engineering (DFT Test) roles from 81 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.