Tech Lead, Formal Verification - Bengaluru, Karnataka, India
Originally posted 3 August 2026 by the employer — open 38 days.
About the role
This role leads formal verification efforts for complex IP and SoC designs. You will focus on Astera Labs' CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies.
What you'll do
- Develop comprehensive formal verification plans from architecture and design specifications.
- Develop and execute formal verification environments, assertions, properties, and checkers.
- Drive proof convergence through advanced abstraction and complexity reduction techniques.
- Evaluate, deploy, and scale formal verification methodologies, flows, and tools across projects.
- Ensure comprehensive design correctness and provide technical leadership and mentorship.
- Support project planning by estimating verification effort, tracking execution, and identifying risks.
What you'll need
- 5-10 years of experience in semiconductor verification, including significant formal verification experience.
- Expert knowledge of SystemVerilog, SVA, Verification planning & closure and ABV verification techniques.
- Hands-on experience with one or more formal verification tools – JG, VCF.
- Experience verifying complex protocols, control logic, and SoC or subsystem-level designs.
- Strong scripting skills in Python, Perl, Tcl, or Shell.
- Experience leading technical efforts or mentoring team members.
Nice to have
- Experience with industry-standard formal verification tools such as JasperGold, VC Formal.
- Experience verifying high-speed protocols and interfaces including PCIe®, UALink™, CXL®, Ethernet, SerDes.
- Knowledge of NoC architectures, cache coherency protocols, memory subsystems, and interconnect fabrics.
- Experience with formal bug hunting, proof-based verification, and coverage-driven verification methodologies.
- Prior experience leading technical teams and mentoring engineers.
- Exposure to simulation, emulation, and the broader verification lifecycle is a plus.
- Track record of contributing to successful silicon tape-outs.
Skills: formal verification, assertion-based verification, SystemVerilog, SVA, JasperGold
This role has been open 37 days — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1123
|
Median days open
56 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1123 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 1123 |
| Open roles in the wider Digital Design & Verification family | 40 | 3042 · 114 employers |
| Median days open | 78 d | 56 d (+22 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: formal verification, assertion-based verification, SystemVerilog, SVA, JasperGold
Who's hiring in this category
- Qualcomm · 98 open roles · median 48 d
- AMD · 97 open roles · median 29 d
- NVIDIA · 95 open roles · median 58 d
- Micron Technology · 53 open roles · median 96 d
- Arm Holdings · 49 open roles · median 65 d
- Marvell Technology · 48 open roles · median 115 d
How we counted: 1123 open Design Verification (Design Verification) roles from 90 employers tracked in the SemiconductorJobs index, counted 10 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.