Tech Lead, Digital Design Engineer - San Jose, California, United States
Originally posted 28 September 2026 by the employer.
About the role
This role involves developing micro-architecture and implementing front-end circuit designs for high-performance network controllers. The Intelligent Connectivity Platform integrates CXL, Ethernet, NVLink, PCIe, and UALink semiconductor technologies.
What you'll do
- Develop micro-architecture and implement front-end circuit designs, including RTL, synthesis, IP integration, and block-level verification.
- Utilize knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, and Ethernet.
- Own block-level design from architecture to GDS.
- Perform silicon bring-up and debug.
What you'll need
- Bachelor’s degree in Electrical Engineering.
- 3+ years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications, or Server, Storage.
- Hands-on knowledge of high-speed protocols including PCIe, Ualink, Esun, and Ethernet.
- Proven front-end design skills covering architecture, RTL, simulations, synthesis, timing closure, GLS, and DFT.
- Experience with Synopsys and/or Cadence digital design tools/flows.
- Knowledge of design for test (DFT).
- Familiarity with UVM based design verification.
- Small-geometry CMOS (≤28nm) design experience.
Nice to have
- Scripting with Python or other equivalent programming languages.
- Development/support for PCIe or Ethernet Switch products.
This role has been open 0 days — well below the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
986
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (986 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 986 |
| Open roles in the wider Digital Design & Verification family | 57 | 3112 · 115 employers |
| Median days open | 19 d | 62 d (−43 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 141 open roles · median 62 d
- AMD · 68 open roles · median 65 d
- Synopsys · 65 open roles · median 24 d
- NXP Semiconductors · 54 open roles · median 72 d
- NVIDIA · 47 open roles · median 53 d
- Analog Devices · 46 open roles · median 37 d
How we counted: 986 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.