SoC Compute/Memory Subsystem Architect - Leixlip, Ireland
$75,200 - $139,700 USD yearly
Originally posted 9 June 2026 by the employer.
This role focuses on defining and driving the architecture of compute complexes and high-performance memory subsystems for IPU/DPU platforms.
About the role
The focus is on architecture for CPU clusters, cache hierarchies, coherency models, and memory subsystems.
What you'll do
- Define and evolve multi-level cache hierarchy and architect coherency models across compute cores, accelerators, and IO subsystems.
- Architect system memory subsystems including DDR/LPDDR interfaces, memory controllers, and scheduling policies.
- Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads, including multi-tenant isolation and security boundaries.
- Architect integration between compute, network, storage, and accelerator subsystems, optimizing data movement.
- Define compute and memory strategies for power efficiency and DVFS scalability, including memory bandwidth throttling and per-subsystem scaling.
- Lead the long-term roadmap for compute and memory evolution across IPU/DPU product generations, defining scaling strategies for core count, frequency, bandwidth, capacity, and cache.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study.
- 10+ years of experience in SoC / CPU / memory subsystem architecture.
- 10+ years of experience in CPU architecture and cache hierarchies.
- 10+ years of experience in Memory subsystems (DDR/HBM, controllers, QoS).
- 10+ years of experience in Coherent/Non-Coherent interconnect architectures.
- 10+ years of experience in system-level performance and PPA tradeoff analysis.
- 10+ years of experience in driving architecture definition from concept to silicon.
Nice to have
- Post Graduate degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study.
- ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.
- Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environments.
- Familiarity with PCIe, CXL, and memory semantics for high performance IO.
- Track record of multi generation architectural ownership and mentoring other architects.
Skills: SoC architecture, compute complex, memory subsystem, cache hierarchies, coherency models, IPU/DPU platforms
This role has been open 117 days — well above the 75-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
442
|
Median days open
75 d
|
Median salary
$236k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (442 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 442 |
| Open roles in the wider Digital Design & Verification family | 65 | 3109 · 114 employers |
| Median days open | 57 d | 75 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $236k |
Skills observed across this category: SoC architecture, compute complex, memory subsystem, cache hierarchies, coherency models, IPU/DPU platforms
Who's hiring in this category
- Qualcomm · 71 open roles · median 82 d
- NVIDIA · 57 open roles · median 59 d
- AMD · 36 open roles · median 61 d
- Arm Holdings · 27 open roles · median 102 d
- Renesas Electronics · 22 open roles · median 59 d
- NXP Semiconductors · 20 open roles · median 104 d
How we counted: 442 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.