Stage Ingénieur : Validation Labo PMIC (F/H) - Toulouse, France
Verification, Validation & Test
Originally posted 23 September 2026 by the employer.
About the role
This internship involves the manual and automated characterization of analog and mixed-signal Power Management ICs (PMIC) within the Advanced Power Systems (APS) team.
What you'll do
- Develop hardware tools for Silicon validation, manual and automated.
- Program optimized software for manual and automated testing with Python.
- Perform IC parametric and functional bench-level measurements.
- Apply AI tools to optimize throughput and result analysis.
- Coordinate with a cross-functional team.
- Drive improvements for validation accuracy, coverage, traceability, and delivery.
What you'll need
- Master's degree / last year of engineering school in Electronics or Electrical Engineering / Microelectronics.
- Proficient in analog, digital, and power circuit fundamentals.
- Excellent technical skills with Lab bench testing.
- Programming skills in Python.
- Good level of English.
Market context
This role has been open 0 days — well below the 23-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
439
|
Median days open
23 d
|
Median salary
$184k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (439 roles · 70 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 439 |
| Open roles in the wider Silicon Validation & Test family | 42 | 2111 · 111 employers |
| Median days open | 22 d | 23 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Who's hiring in this category
- Teradyne · 49 open roles · median 5 d
- Infineon Technologies · 37 open roles · median 32 d
- Renesas Electronics · 34 open roles · median 33 d
- Micron Technology · 26 open roles · median 23 d
- Qualcomm · 25 open roles · median 20 d
- AMD · 20 open roles · median 28 d
How we counted: 439 open Silicon Test Engineering (DFT Test) roles from 70 employers tracked in the SemiconductorJobs index, counted 23 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.