Stage Ingénieur : Techniques de vérification basse consommation utilisant l'UVM, les preuves formelles et les capacités de l'IA (H/F)
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This intern role focuses on improving the verification of Power Management in NFC components. The scope involves enhancing digital verification for Secure Transactions and Identification products.
What you'll do
- Analyze and understand SoC power-management architecture, including power-gating, resets, clocking interactions, and wreal models.
- Understand the SystemVerilog testbench, develop, and execute test scenarios.
- Implement SystemVerilog assertions (SVA).
- Analyze simulation results, waveform traces, and coverage metrics.
- Use Jasper Formal Proof to verify correctness of Power controller finite-state machines, safety conditions, reset and isolation sequencing, and deadlocks.
- Investigate how AI/ML tools can support verification activities.
What you'll need
- Bac + 5 years, last Engineering School in Integrated Circuits, Integrated Electronics Systems, Electronics, Micro-Electronics, or Embedded Systems.
- Digital design knowledge.
- SystemVerilog knowledge.
- Verification concepts knowledge.
- Good English proficiency.
Skills: UVM, SystemVerilog, Formal Verification, Jasper Formal Proof, Power Management, NFC
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1150
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (1150 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 1150 |
| Open roles in the wider Digital Design & Verification family | 148 | 3066 · 114 employers |
| Median days open | 91 d | 60 d (+31 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, SystemVerilog, Formal Verification, Jasper Formal Proof, Power Management, NFC
Who's hiring in this category
- Qualcomm · 106 open roles · median 50 d
- AMD · 102 open roles · median 34 d
- NVIDIA · 89 open roles · median 68 d
- Synopsys · 62 open roles · median 17 d
- Micron Technology · 54 open roles · median 101 d
- SiFive · 52 open roles · median 49 d
How we counted: 1150 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.