Stage Ingénieur : Conception pour le test (DFT) / Conception numérique (F/H) - Sophia-Antipolis (Valbonne)
Verification, Validation & Test
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This internship focuses on Design-for-Test (DFT) activities within the Digital SoC Design team, specifically automating the Design For Test process for SoCs.
What you'll do
- Understand the Computer-Aided Design (CAD) environment and challenges in advanced design automation.
- Use AI and scripting to automate DFT IP integration in a System-on-Chip (SoC) or sub-system.
- Use AI and scripting to automate DFT integration verification.
- Release, document, and maintain the developed design flow.
What you'll need
- Master's degree in Electrical Engineering, Microelectronics, Computer Engineering, or a related field.
- Strong interest in digital integrated circuit design, verification, and test methodologies.
- Experience with RTL design and simulation using Verilog.
- Good understanding of digital logic design and semiconductor fundamentals.
- Knowledge of Design-for-Test (DFT) concepts.
- Familiarity with scripting and programming languages such as Python, Perl, Tcl.
Nice to have
- Exposure to production testing.
Market context
This role has been open 0 days — well below the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
215
|
Median days open
61 d
|
Median salary
$199k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | NXP Semiconductors | All employers we track in this specialty (215 roles · 51 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 215 |
| Open roles in the wider Digital Design & Verification family | 148 | 3066 · 114 employers |
| Median days open | 74 d | 61 d (+13 d vs this employer) |
| Median salary (USD postings) | — | $199k |
Who's hiring in this category
- AMD · 33 open roles · median 48 d
- Qualcomm · 25 open roles · median 81 d
- NVIDIA · 17 open roles · median 70 d
- NXP Semiconductors (this employer) · 17 open roles · median 74 d
- Micron Technology · 10 open roles · median 113 d
- Intel Corporation · 8 open roles · median 53 d
How we counted: 215 open DFT Engineering (DFT Test) roles from 51 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Sophia-Antipolis (Valbonne)
On-site
Internship
13 days ago