Staff, VLSI Design Engineering (Verification) with 8-12 years of experience - Bengaluru, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves leading functional verification closure for complex IP blocks and fullchip designs. You will be instrumental in ensuring design quality and silicon success.
What you'll do
- Lead the development and execution of comprehensive test plans and verification strategies for IP blocks, sub-systems, and SoC designs.
- Design and implement verification environments using UVM frameworks.
- Develop reusable verification components including bus functional models, monitors, checkers, and scoreboards.
- Drive functional coverage-driven verification closure.
- Develop and maintain System Verilog Assertions (SVA) for design verification.
- Debug and perform root-cause analysis of design failures.
What you'll need
- 8 to 12 years of experience in VLSI design verification.
- Bachelor's degree in Electronics and Communication Engineering (ECE), VLSI, or Electrical Engineering.
- Advanced proficiency in C, Verilog, System Verilog, and UVM.
- Hands-on experience with Xcellium, Verdi, and JasperGold formal verification tools.
- Expertise across the complete verification lifecycle, including planning, testbench development, test case development, regression management, coverage analysis, debugging, and sign-off.
- Proven ability to lead technical projects.
Nice to have
- Experience with NAND flash memory protocols and memory design verification.
- Experience with formal verification methodologies and assertion-based verification.
Skills: UVM, SystemVerilog, test plans, functional coverage, formal verification
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1138
|
Median days open
57 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (1138 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1138 |
| Open roles in the wider Digital Design & Verification family | 15 | 3022 · 114 employers |
| Median days open | 51 d | 57 d (−6 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, SystemVerilog, test plans, functional coverage, formal verification
Who's hiring in this category
- Qualcomm · 107 open roles · median 51 d
- AMD · 98 open roles · median 33 d
- NVIDIA · 90 open roles · median 66 d
- Micron Technology · 56 open roles · median 97 d
- Synopsys · 56 open roles · median 24 d
- SiFive · 51 open roles · median 45 d
How we counted: 1138 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.