Staff VLSI Design Engineer - Seoul, South Korea
Originally posted 23 September 2026 by the employer.
About the role
This Staff VLSI Design Engineer will be responsible for all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis.
What you'll do
- Perform RTL design and verification in Verilog, RTL linting, and clock domain crossing (CDC) analysis.
- Execute design integration, synthesis, DFT, timing analysis, and closure.
- Balance design trade-offs with modularity, scalability, power, area, and performance.
- Interface with internal and external teams/customers to drive necessary technical specifications and features.
- Participate in Post-Si evaluation and debug.
- Provide technical guidance and mentoring of junior engineers.
What you'll need
- Master of Science in Electrical Engineering or related field, plus 6-8 years of relevant experience.
- Experience with chip level integration, chip lead, and full product life cycle (requirements, design, implementation, test) of Logic design.
- Working knowledge of the entire Logic design flow from RTL to GDSII (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion, place-and-route, clock tree synthesis, extraction, static timing analysis, physical verification).
- Working knowledge of NAND flash memory cell device operations and algorithms for program/read/erase.
Nice to have
- Experience developing digital circuit designs for low power operating conditions.
- Working knowledge of device physics and process.
- Working knowledge of NAND Flash memory design including Analog, Core, Datapath, and IO circuits.
- Proficiency with Synopsys Design Compiler, Cadence Genus, or Cadence RTL Compiler for synthesis.
- Proficiency with Synopsys Primetime or Cadence Tempus for static timing.
- Proficiency with Synopsys ICC, Cadence Encounter, or Innovus for place and route.
- Familiarity with revision control tools and EDA standard formats like Liberty (timing model) and SDC (Synopsys Design Constraints).
- Programming experience in C, C++, Python, or Perl.
Skills: NAND Flash memory, RTL design, verification, logic synthesis, timing analysis
This role has been open 12 days — well below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SanDisk | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 287 |
| Median days open | 32 d | 69 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: NAND Flash memory, RTL design, verification, logic synthesis, timing analysis
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk (this employer) · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.