Staff Verification Engineer - Chandler, United States
Originally posted 18 September 2026 by the employer — open 2 days.
About the role
This role involves the verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP. You will drive the successful development, integration, and sign-off of complex mixed-signal power chips.
What you'll do
- Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMIC designs.
- Develop and implement comprehensive verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200).
- Lead debugging activities for complex analog blocks including switched-mode regulators, Linear Dropout (LDO) regulators, and mixed-signal interfaces.
- Set up and optimize Gate-Level Simulation (GLS) flows, correlating with RTL simulation results to identify and resolve discrepancies.
- Conduct in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
- Troubleshoot and debug complex design issues involving interactions between analog and digital domains using simulation and measurement techniques.
What you'll need
- Experience as a mixed-signal verification engineer.
- Experience with verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP.
- Experience designing and architecting mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration.
- Experience developing and implementing verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards (ISO 26262, AEC-Q200).
- Experience with Gate-Level Simulation (GLS) flows and correlating with RTL simulation results.
- Experience conducting in-depth RTL and Gate-Level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
Skills: mixed-signal verification, verification environments, AMS model integration, automotive safety standards, RTL and Gate-Level simulations
This role has been open 1 day — well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1133
|
Median days open
59 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Renesas Electronics | All employers we track in this specialty (1133 roles · 93 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1133 |
| Open roles in the wider Digital Design & Verification family | 84 | 3011 · 114 employers |
| Median days open | 26 d | 59 d (−33 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: mixed-signal verification, verification environments, AMS model integration, automotive safety standards, RTL and Gate-Level simulations
Who's hiring in this category
- Qualcomm · 103 open roles · median 54 d
- AMD · 100 open roles · median 32 d
- NVIDIA · 89 open roles · median 66 d
- Synopsys · 58 open roles · median 21 d
- Micron Technology · 56 open roles · median 99 d
- SiFive · 52 open roles · median 47 d
How we counted: 1133 open Design Verification (Design Verification) roles from 93 employers tracked in the SemiconductorJobs index, counted 20 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.