Staff. Physical Design Engineer
$140,000 - $210,000 USD yearly
Originally posted 26 June 2026 by the employer.
About the role
As a Staff Physical Design Engineer at Qualcomm, you will define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
What you'll do
- Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance and low-power products. - Create architectures, circuit specifications, logic designs, and system simulations based on system-level requirements. - Collaborate across hardware and software architecture teams to develop and execute implementation strategies meeting system requirements. - Evaluate process flow aspects from high-level design to synthesis, place and route, timing and power, and verification, or custom circuit design/layout flows. - Utilize tools and applications including RTL to GDS Flow and Virtuoso to execute architecture and design of blocks, SoCs, or IC packages. - Author detailed technical documentation for EDA, IP, and ASIC projects.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related experience; OR Master's degree with 1+ year of experience; OR a PhD. - Experience evaluating synthesis, place and route, and timing and power. - Experience with RTL to GDS Flow or Virtuoso for block/SoC or IC Package design. - Experience developing technical documentation for EDA, IP, or ASIC projects.
Nice to have
- Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science. - 3 years of ASIC design, verification, validation, integration, or related work experience. - 2 years of experience with architecture and design tools. - 2 years of experience with scripting tools and programming languages. - 2 years of experience with design verification methods.
Skills: ASIC design, Physical Design Engineer, place and route, timing and power, RTL to GDS Flow
This role has been open 118 days — well above the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
664
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (664 roles · 79 employers) |
|---|---|---|
| Open roles in this specialty | 122 | 664 |
| Open roles in the wider Physical Implementation family | 167 | 1489 · 110 employers |
| Median days open | 45 d | 62 d (−17 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC design, Physical Design Engineer, place and route, timing and power, RTL to GDS Flow
Who's hiring in this category
- Qualcomm (this employer) · 119 open roles · median 45 d
- AMD · 61 open roles · median 27 d
- Intel Corporation · 40 open roles · median 15 d
- NVIDIA · 38 open roles · median 67 d
- Synopsys · 38 open roles · median 36 d
- Broadcom · 35 open roles · median 101 d
How we counted: 664 open Physical Design (Physical Design) roles from 79 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.