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Arm Holdings

Staff PCB - Package co-design Engineer - Chandler, Arizona, United States

Arm Holdings Chandler, Arizona, United States 2 months ago
Digital Design & SoC Architecture

$198,100 - $268,000 USD yearly

Originally posted 10 August 2026 by the employer.

About the role

This role involves specializing in PCB to silicon packaging co-design to join Arm’s Packaging, Boards and Multiphysics team, focusing on aspects like chip packaging and System-on-Chip (SoC) integration for systems incorporating Arm processors.

What you'll do

  • Collaborate with engineering teams to specify, evaluate, analyze, and develop solutions for efficient PCB and silicon package integration.
  • Drive PCB development alongside the chip packaging team, including brainstorming breakout and routing strategies, design rules, and layer optimization.
  • Provide timescale estimates and justifications into the program team.
  • Analyze and optimize signal paths to ensure signal quality, minimize noise, and prevent signal degradation at high speeds.
  • Evaluate package pinout options against PCB routability, SI/PI performance, layer count, manufacturability, and cost.
  • Support early silicon and board architecture planning, including component placement, form-factor constraints, PDN strategy, and routing feasibility.

What you'll need

  • Strong understanding of electronics and embedded compute systems.
  • Familiarity with different IC packaging technologies and their impact on PCB design.
  • Experience collaborating with chip packaging teams and influencing SoC device pin-outs.
  • Detailed knowledge of high-speed design and interface standards (e.g., PCIe and LPDDR memory technologies).
  • Expertise in escape routing analysis of high density SoCs and ability to provide IO count estimates for given stack-up and design rule sets.
  • Extensive knowledge of Signal and Power Integrity analysis techniques from both board design and chip packaging perspectives.
  • Understanding of the PCB fabrication process (PTH and HDI), stackup/VIA topologies, and substrate materials.
  • Proficiency in the use of EDA tools for schematic entry and PCB layout (Cadence OrCAD & Allegro).
Market context

This role has been open 68 days — well above the 50-day median for Hardware Systems Engineering roles.

Hardware Systems Engineering · AI ML Hardware

Open roles in category
966
Median days open
50 d
Median salary
$156k
See the full market breakdown ▾Category comparison, and who else is hiring
How Arm Holdings compares in Hardware Systems Engineering hiring
Metric Arm Holdings All employers we track in this specialty (966 roles · 102 employers)
Open roles in this specialty 4 966
Open roles in the wider Software, Firmware & Systems family 83 6114 · 145 employers
Median days open 86 d 50 d (+36 d vs this employer)
Median salary (USD postings) — $156k

Who's hiring in this category

  • Intel Corporation · 74 open roles · median 35 d
  • KLA Corporation · 65 open roles · median 43 d
  • Teradyne · 57 open roles · median 29 d
  • NVIDIA · 52 open roles · median 67 d
  • Applied Materials · 50 open roles · median 65 d
  • AMD · 47 open roles · median 49 d

How we counted: 966 open Hardware Systems Engineering (AI ML Hardware) roles from 102 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.

Apply now
Chandler, Arizona, United States
On-site
$198,100 - $268,000 USD yearly
2 months ago

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