Wireless SoC Design Engineer - Sunnyvale, United States
Originally posted 16 October 2026 by the employer.
Design CPU-based subsystems for high performance, low power wireless SoCs.
About the role
This role involves designing CPU-based subsystems for high performance, low power wireless SoCs. You will work on SoCs that meet power, performance, and area goals for Apple devices, with a particular focus on low power metrics.
What you'll do
- Develop SoCs to meet power, performance, and area goals for Apple devices
- Engage in hardware/software/power partitioning discussions with software, firmware, and platform engineering teams
- Integrate industry standard and custom hardware IPs into SoCs
What you'll need
- BS with 10+ years relevant experience
- Familiarity with the ASIC design flow
- Knowledge of digital design, SoC architecture, and HDL languages like Verilog
Nice to have
- Experience writing micro-architecture specifications and converting them to design
- Exposure to design methodologies and industry standard EDA tools
- Experience with AXI/AHB bus fabric and processor sub-systems
- Understanding of UPF and low-power design & implementation techniques
Skills: ASIC design flow, digital design, Verilog, SoC architecture, micro-architecture
This role has been open 0 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1024
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1024 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1024 |
| Open roles in the wider Digital Design & Verification family | 77 | 3202 · 115 employers |
| Median days open | 0 d | 61 d (−61 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC design flow, digital design, Verilog, SoC architecture, micro-architecture
Who's hiring in this category
- Qualcomm · 140 open roles · median 63 d
- Synopsys · 86 open roles · median 31 d
- AMD · 71 open roles · median 37 d
- Analog Devices · 47 open roles · median 49 d
- NVIDIA · 44 open roles · median 59 d
- NXP Semiconductors · 42 open roles · median 85 d
How we counted: 1024 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.