Staff Package Design Engineer - Austin, Texas, United States
Originally posted 12 May 2026 by the employer.
Design packaging solutions spanning WLCSP, wire-bond QFN, and flip-chip architectures using Cadence SiP Layout.
About the role
Cirrus Logic is seeking a Staff Package Design Engineer in Austin, TX to develop packaging solutions for products including amplifiers, codecs, and DSPs. The role covers package design technologies spanning wire-bond QFN, WLCSP, and flip-chip designs.
What you'll do
- Design package layouts, stack-ups, drawings, models, simulations, and documentation to verify compliance with design standards. - Interface with global IC and board design teams to define package requirements from electrical, thermal, and mechanical standpoints. - Utilize AutoCAD, GDS tools, Siemens Fast3D, and Cadence SiP Layout to execute physical design, electrical simulation, and manufacturing validation, including die bump array and BGA integration refinement. - Collaborate with designers, customers, and OSATs to establish and maintain design rules for WLCSP, wire-bond, and other package architectures. - Perform DFM checking and modifications to improve assembly yield, prevent manufacturing issues, and resolve interface issues between parts and PCBs. - Develop and promote automation processes across the package design flow.
What you'll need
- B.S. or higher degree in Mechanical or Electrical Engineering. - 5+ years of experience designing for manufacturability. - Practical experience as a Cadence SiP Layout user. - Proficiency using AutoCAD. - Knowledge of packaging technologies, materials, package substrate design, and assembly rules. - Understanding of electrical simulation results on package designs.
Nice to have
- Familiarity with PCB and die mechanical layout tools, such as Siemens Xpedition, Allegro PCB, or Cadence Virtuoso. - Electrical simulation skills. - Experience using Siemens Fast3D. - Experience using Siemens Calibre DRV.
Skills: package design, WLCSP, SiP Layout, die bump array, DFM checking, electrical simulation
This role has been open 164 days — well above the 59-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
208
|
Median days open
59 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cirrus Logic | All employers we track in this specialty (208 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 208 |
| Open roles in the wider Process, Fab & Equipment family | 5 | 10039 · 106 employers |
| Median days open | 164 d | 59 d (+105 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: package design, WLCSP, SiP Layout, die bump array, DFM checking, electrical simulation
Who's hiring in this category
- Renesas Electronics · 30 open roles · median 36 d
- Infineon Technologies · 25 open roles · median 40 d
- Micron Technology · 21 open roles · median 39 d
- onsemi · 16 open roles · median 29 d
- Monolithic Power Systems · 11 open roles · median 218 d
- Intel Corporation · 9 open roles · median 109 d
How we counted: 208 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.