Principal Engineer, Package Design - Santa Clara, CA, United States
$164,800 - $226,600 USD yearly
Originally posted 8 June 2026 by the employer. Relisted by the employer on 27 August 2026.
MEMS-based timing products integrating custom MEMS and CMOS components.
About the role
The Principal Engineer, Package Design is responsible for the specification, design, development, and qualification of custom packaging technology for MEMS-based timing products. Packaging technologies encompass QFN, WLCSP, ceramic, substrate-based, and multi-chip modules integrating custom MEMS and CMOS components.
What you'll do
- Develop new packaging technology and lead package design, development, and release-to-production for MEMS-based timing solutions. - Develop, manage, and analyze DoEs conducted locally and overseas. - Manage development and prototyping activities with OSATs to bring new custom package designs into production. - Ensure new packaging technologies meet required performance, reliability, and quality standards. - Lead troubleshooting activities related to package design and performance.
What you'll need
- M.S. or Ph.D. degree in Mechanical Engineering, Material Science, or a relevant field. - 10+ years of experience in semiconductor IC packaging technology and methodology. - Experience managing overseas OSATs to bring products into production. - Knowledge of leadframe-based, flip-chip, and substrate-based packages. - Hands-on experience with flip-chip and bumping technologies. - Understanding of thermal, stress, and electrical considerations in package design, along with hands-on experience using CAD software.
Nice to have
- Understanding of thermal, mechanical, and electrical modeling for semiconductor packages. - Understanding of material characterization techniques including DMA, TMA, and TGA. - Experience with AutoCAD.
Skills: semiconductor IC packaging, leadframe-based, flip-chip, substrate-based, bumping technologies, OSATs
This role has been open 136 days — well above the 59-day median for Packaging Engineering roles.
Packaging Engineering · Packaging
|
Open roles in category
208
|
Median days open
59 d
|
Median salary
$166k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiTime | All employers we track in this specialty (208 roles · 41 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 208 |
| Open roles in the wider Process, Fab & Equipment family | 18 | 10080 · 106 employers |
| Median days open | 115 d | 59 d (+56 d vs this employer) |
| Median salary (USD postings) | — | $166k |
Skills observed across this category: semiconductor IC packaging, leadframe-based, flip-chip, substrate-based, bumping technologies, OSATs
Who's hiring in this category
- Renesas Electronics · 30 open roles · median 36 d
- Infineon Technologies · 25 open roles · median 40 d
- Micron Technology · 21 open roles · median 39 d
- onsemi · 16 open roles · median 29 d
- Monolithic Power Systems · 11 open roles · median 218 d
- Intel Corporation · 9 open roles · median 109 d
How we counted: 208 open Packaging Engineering (Packaging) roles from 41 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.