Staff Layout Engineer - Singapore-Yishun, Singapore
Originally posted 5 August 2026 by the employer.
About the role
This role is for a Staff Layout Engineer within the Library Group, focusing on circuit design for memory, I/O, and Standard Cells.
What you'll do
- Apply layout guidelines, process rules, and technical requirements for quality layout of standard cells, I/O, and memories.
- Schedule timelines and perform layout floor-planning.
- Complete quality layout and verification within the planned schedule.
- Get up to speed quickly on new methodologies and communicate effectively with the library team.
- Perform memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
- Lead new technology reviews to compile documentation for layout methodology, flow, and guidelines.
What you'll need
- Minimum 8 years of experience in IC Layout.
- Strong knowledge of Cadence layout, Cadence schematic capture, CALIBRE, and Hercules verification tools.
- Strong layout knowledge in submicron processes, including 16nm, 7nm, 5nm, 2nm, and A14.
- Experience in digital layout (standard cell, memory, I/O).
- Strong experience in memory layout design and physical verifications, including LVS, DRC, ERC, Antenna, and Electro Migration in CMOS processes.
- Experience with Cadence Layout tools VIRTUOSO (XL, VXL, or EXL) and CALIBRE verification tools.
- Good experience in Floor-planning, hierarchy layout, and chip integration.
Nice to have
- Experience in analog layout.
- Experience in memory compiler.
- Knowledge of Script Programming and SKILL Programming.
- Ability to lead or train a team of junior engineers.
- Good knowledge of memory layout topology.
Skills: IC Layout, Cadence layout, CALIBRE verification, submicron processes, memory layout design
This role has been open 60 days — below the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 287 |
| Median days open | 51 d | 69 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: IC Layout, Cadence layout, CALIBRE verification, submicron processes, memory layout design
Who's hiring in this category
- Micron Technology · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom (this employer) · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.