Staff Interop Validation Engineer – AI Data Center Interconnect - Santa Clara, CA, United States
Originally posted 23 October 2026 by the employer.
Validate PAM4 DSPs and optical interconnects for cloud data center networks.
About the role
Marvell Technology is seeking a Staff Interop Validation Engineer in Santa Clara, CA to evaluate DSP hardware and software features and implement qualification plans. The role focuses on PAM4 DSPs for high-speed optical interconnects in cloud data centers and carrier networks.
What you'll do
- Evaluate hardware and software features from DSP and develop implementation plans for qualification and testing. - Collaborate with vendors and manufacturers to define and develop test plans for optical modules and DSP chips. - Automate optical test plans and qualify optical modules from different vendors across various switches. - Build engineering dashboards and regular status reports to track optical module and DSP qualification progress, interop lab readiness, and performance metrics. - Adapt and benchmark open-weight language models to review lab data, analyze electrical and optical measurements, and classify failure causes. - Build end-to-end automation pipelines using Python scripts and statistical checks across lab logs, specs, and prior test records.
What you'll need
- Bachelor's degree in Computer Science, Electrical Engineering, or related field with 3-5 years of related professional experience, or a Master's degree/PhD with 2-3 years of experience. - 2+ years of experience with transceivers and IEEE standards. - 2+ years of experience developing test scripts for validation and characterization. - 1+ years of experience working with networking protocols and technologies.
This role has been open 0 days — well below the 35-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
559
|
Median days open
35 d
|
Median salary
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (559 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 18 | 559 |
| Open roles in the wider Silicon Validation & Test family | 59 | 2240 · 112 employers |
| Median days open | 31 d | 35 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 76 open roles · median 28 d
- Infineon Technologies · 46 open roles · median 39 d
- Renesas Electronics · 46 open roles · median 29 d
- Qualcomm · 31 open roles · median 35 d
- Micron Technology · 28 open roles · median 39 d
- Texas Instruments · 26 open roles · median 30 d
How we counted: 559 open Silicon Test Engineering (DFT Test) roles from 78 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.