Staff HSIO Digital & Mixed Signal Design Engineer - San Jose, California, United States
$163,000 - $253,000 USD yearly
Originally posted 13 October 2026 by the employer.
About the role
What you'll do
- Define architecture, silicon design, algorithm and software development, platform integration, performance optimization, and test.
- Collaborate effectively with system and analog teams on the digital design flow.
What you'll need
- BS in Electrical Engineering with 10+ years of experience or MS in Electrical Engineering with 8+ years of experience or PhD in Electrical Engineering with 5+ years of experience.
- Hands-on experience with HSIO PHY IP (e.g., UCIe, BOW, PCIe).
- Deep understanding of high-speed serial interconnect protocols and associated design trade-offs.
- Strong understanding of how analog and mixed-signal design and verification impact digital-on-top development flows.
- Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs.
Skills: HSIO PHY IP, UCIe, BOW, PCIe, high-speed serial interconnect, digital design flow
This role has been open 1 day — well below the 81-day median for High-Speed IO/SerDes Design roles.
High-Speed IO/SerDes Design · Serdes Highspeed
|
Open roles in category
241
|
Median days open
81 d
|
Median salary
$177k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Samsung Semiconductor | All employers we track in this specialty (241 roles · 48 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 241 |
| Open roles in the wider Analog & Mixed-Signal family | 9 | 1414 · 104 employers |
| Median days open | 97 d | 81 d (+16 d vs this employer) |
| Median salary (USD postings) | — | $177k |
Skills observed across this category: HSIO PHY IP, UCIe, BOW, PCIe, high-speed serial interconnect, digital design flow
Who's hiring in this category
- Synopsys · 31 open roles · median 29 d
- AMD · 30 open roles · median 38 d
- Cadence Design Systems · 19 open roles · median 187 d
- Qualcomm · 19 open roles · median 61 d
- Micron Technology · 13 open roles · median 74 d
- Apple · 12 open roles · median 15 d
How we counted: 241 open High-Speed IO/SerDes Design (Serdes Highspeed) roles from 48 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Analog & Mixed-Signal family row. Figures refresh nightly.