Staff Formal Verification Engineer - India
Originally posted 15 September 2026 by the employer — open 2 days.
Join SiFive to own verification strategy and execution for complex out-of-order (OOO) processor Blocks.
About the role
As a Staff Formal Verification Engineer, you will own verification strategy and execution for complex out-of-order (OOO) processor Blocks. This role focuses on the formal verification of RISC-V out-of-order (OOO) processors.
What you'll do
- Identify blocks suitable for applying Formal Verification.
- Create Formal Test-plan for blocks identifying properties to be implemented and sign-off metrics.
- Implement and maintain Formal Verification environments in Chisel.
- Apply various FV techniques to reduce complexity and prove correctness of DUT.
- Debug RTL to identify causes of failure scenarios.
- Maintain and extend assertion libraries.
What you'll need
- 7+ years of experience in Formal Verification of Digital Hardware Design.
- Extensive experience with Formal Abstraction Techniques and sign-off process.
- Familiarity with industry-standard Formal Verification Tools, such as VC Formal, JasperGold.
- Knowledge of Hardware Description and Verification Languages, such as VHDL, Verilog/ SystemVerilog.
- Interest in Processors and Digital systems.
- Strong reasoning skills and attention to detail.
Nice to have
- Knowledge of Object-oriented Programming.
Skills: formal verification, formal test-plan, VC Formal, JasperGold, assertion libraries
This role has been open 2 days — well below the 56-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1122
|
Median days open
56 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | SiFive | All employers we track in this specialty (1122 roles · 92 employers) |
|---|---|---|
| Open roles in this specialty | 51 | 1122 |
| Open roles in the wider Digital Design & Verification family | 82 | 3007 · 114 employers |
| Median days open | 44 d | 56 d (−12 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: formal verification, formal test-plan, VC Formal, JasperGold, assertion libraries
Who's hiring in this category
- Qualcomm · 104 open roles · median 53 d
- AMD · 99 open roles · median 33 d
- NVIDIA · 90 open roles · median 65 d
- Micron Technology · 56 open roles · median 96 d
- Synopsys · 54 open roles · median 23 d
- SiFive (this employer) · 51 open roles · median 44 d
How we counted: 1122 open Design Verification (Design Verification) roles from 92 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.