Staff Engineer, STA - Bengaluru, India

Originally posted 6 October 2026 by the employer.

About the role

The Staff Engineer, STA is responsible for ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners. This role owns timing constraint development and validation, performs detailed setup/hold and variation-aware analysis, and partners closely with Synthesis, CTS, Physical Design, and Design teams to debug violations and drive ECO-based optimizations through tapeout.

What you'll do

• Perform full-chip and block-level Static Timing Analysis (STA) across all modes and corners.
• Analyze and debug setup, hold, recovery, removal, clock gating, and signal integrity-related timing violations.
• Develop and maintain timing constraints including SDC creation, validation, and signoff readiness.
• Drive timing closure through ECO implementation and timing optimization.
• Analyze timing impact due to process, voltage, and temperature variations.
• Support timing signoff for pre-layout and post-layout stages.

What you'll need

• 4–12 years of experience in Static Timing Analysis (STA) and timing closure for block and/or full-chip designs.
• Hands-on experience in setup/hold analysis, path-based analysis, OCV/AOCV/POCV, derates, and MMMC concepts.
• Strong knowledge of SDC, timing exceptions, false paths, multicycle paths, and case analysis.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime or Cadence Tempus.
• Good scripting skills in Tcl, Perl, or Python.
• Ability to analyze and resolve timing violations independently.

Nice to have

• Exposure to low-power timing analysis and UPF/CPF-aware STA.
• Familiarity with SI-aware timing, Crosstalk analysis, and IR-drop-aware timing closure.
• Knowledge of advanced technology nodes and variation-aware signoff methodologies.
• Exposure to automation and flow development.

Skills: Static Timing Analysis, STA, timing closure, SDC, PrimeTime