Staff Engineer - SoC Power Architecture - Bangalore, India
Originally posted 22 September 2026 by the employer — open 0 days.
About the role
This role involves driving power-efficient architectures for SoCs, focusing on optimizing dynamic power, Vmin reduction, and leakage power.
What you'll do
- Explore and optimize SoC-level power architecture features and their dependencies with IP blocks.
- Conduct energy and latency sensitivity studies of dynamic power reduction techniques like DVFS, clock gating, power gating, and micro/macro power collapse.
- Analyze and optimize Vmin margins, power-performance tradeoffs, and silicon robustness.
- Drive leakage reduction and low-power design techniques across advanced process nodes.
- Evaluate efficient techniques for managing voltage droops, overshoots, thermal, and electrical limits.
- Develop MATLAB models to quantify PPA KPIs of power architecture features and use SPICE simulations to optimize SoC/System-level architecture.
What you'll need
- Bachelor's/Master's degree in Electrical/Electronics Engineering or a related field.
- 8 years of experience in SoC Power Architecture, Energy Management, and Low-Power Design.
- Strong expertise in Dynamic Power Optimization.
- Strong expertise in Vmin Analysis and Margining.
- Strong expertise in Leakage Power Reduction.
- Strong expertise in Low-Power Design Techniques.
- Strong expertise in PDN/Power Integrity Analysis.
- Strong expertise in DVFS, Clock Gating, Power Gating.
- Hands-on experience with MATLAB Modeling.
- Hands-on experience with SPICE Simulations.
- Hands-on experience with Lab power/perf data crunching.
Skills: SoC Power Architecture, dynamic power optimization, Vmin reduction, leakage power, DVFS, power gating
This role has been open 0 days — well below the 67-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
448
|
Median days open
67 d
|
Median salary
$237k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (448 roles · 63 employers) |
|---|---|---|
| Open roles in this specialty | 69 | 448 |
| Open roles in the wider Digital Design & Verification family | 391 | 3066 · 114 employers |
| Median days open | 81 d | 67 d (+14 d vs this employer) |
| Median salary (USD postings) | — | $237k |
Skills observed across this category: SoC Power Architecture, dynamic power optimization, Vmin reduction, leakage power, DVFS, power gating
Who's hiring in this category
- Qualcomm (this employer) · 68 open roles · median 81 d
- NVIDIA · 60 open roles · median 46 d
- AMD · 35 open roles · median 74 d
- Arm Holdings · 27 open roles · median 89 d
- Renesas Electronics · 20 open roles · median 68 d
- NXP Semiconductors · 19 open roles · median 91 d
How we counted: 448 open SoC/Chip Architecture (SOC Architecture) roles from 63 employers tracked in the SemiconductorJobs index, counted 22 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.