Digital IC Design- Intern - Yokneam, Israel
Originally posted 4 October 2026 by the employer.
About the role
This internship involves contributing to the Design-for-Test (DFT) team as an ATPG Engineer, focusing on the development and implementation of test methodologies for complex SoC designs.
What you'll do
- Assist in scan insertion and ATPG flow setup for digital designs.
- Generate and validate test patterns for stuck-at and transition faults.
- Analyze fault coverage and identify areas for improvement.
- Support silicon bring-up and debug of test-related issues.
- Collaborate with design and verification teams to ensure testability requirements are met.
- Document methodologies, results, and best practices.
What you'll need
- 2nd/3rd year Student for B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
- Basic understanding of digital logic design and VLSI concepts.
- Familiarity with scripting languages (e.g., Python, Perl, or TCL).
- Strong analytical and problem-solving skills.
Nice to have
- Exposure to EDA tools such as Synopsys TetraMAX, Cadence Modus, or similar.
Skills: digital logic design, VLSI concepts, EDA tools, Synopsys TetraMAX, Cadence Modus
This role has been open 0 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
968
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (968 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 13 | 968 |
| Open roles in the wider Digital Design & Verification family | 32 | 3108 · 114 employers |
| Median days open | 16 d | 61 d (−45 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: digital logic design, VLSI concepts, EDA tools, Synopsys TetraMAX, Cadence Modus
Who's hiring in this category
- Qualcomm · 139 open roles · median 58 d
- Synopsys · 68 open roles · median 24 d
- AMD · 65 open roles · median 46 d
- NXP Semiconductors · 47 open roles · median 80 d
- Analog Devices · 45 open roles · median 39 d
- NVIDIA · 45 open roles · median 58 d
How we counted: 968 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 4 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.