Originally posted 10 November 2026 by the employer.
About the role
Plan, build, and execute the verification of new and existing features for AMD graphics processor IP.
What you'll do
- Define and own the emulation architecture, methodology roadmap, and platform strategy for complex SoCs, including partitioning, interconnects, clocking, debug infrastructure, and high-speed interfaces.
- Lead the development and deployment of emulation platforms, including RTL adaptation, implementation flows, verification infrastructure, regression environments, and system-level debug capabilities.
- Collaborate across architecture, RTL design, verification, emulation, software, and firmware teams to enable early hardware validation, software bring-up, and functional coverage goals.
- Provide technical leadership for emulation engineers through mentoring, design reviews, best-practice development, project planning, and execution of program milestones.
- Establish engineering processes, implementation methodologies, documentation standards, and continuous improvement initiatives.
- Represent the emulation team in architecture and program reviews, partnering with EDA and FPGA tool vendors to resolve complex technical challenges.
What you'll need
- Bachelor's or Master's degree in Computer Engineering or Electrical Engineering.
Nice to have
- Experience leading emulation efforts for large-scale semiconductor programs.
- SystemVerilog and/or Verilog design and validation experience.
- Hands-on experience with Synopsys ZeBu and/or Cadence Palladium platforms.
- Experience in FPGA design, implementation, and SoC prototyping.
- Knowledge of SoC bring-up and high-speed interfaces such as PCIe, DDR, Ethernet, USB, and HBM.
- Proficiency with AMD/Xilinx Vivado and Vitis toolchains.
- Expertise in design reviews, modeling ASIC components not usable on emulators, and coverage and power analysis on emulators.
- Understanding of modern SoC architectures, including CPUs, cache hierarchies, memory subsystems, NoC/interconnects, and I/O protocols such as AXI, ACE, CHI, PCIe, and DDR.
Skills: Emulation, Palladium, Zebu, FPGA Prototyping, SystemVerilog, Vivado
More semiconductor jobs: AMD jobs · Verification engineer jobs · California jobs
First seen in our index 0 days ago, well below the 61-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1353
|
Median days since first seen
61 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1353 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 86 | 1353 |
| Open roles in the wider Digital Design & Verification family | 273 | 3538 · 119 employers |
| Median days since first seen | 70 d | 61 d (−9 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: Emulation, Palladium, Zebu, FPGA Prototyping, SystemVerilog, Vivado
Who's hiring in this category
- Qualcomm · 118 open roles · median 53 d
- Apple · 112 open roles · median 14 d
- NVIDIA · 105 open roles · median 75 d
- AMD (this employer) · 84 open roles · median 71 d
- Synopsys · 74 open roles · median 55 d
- SiFive · 57 open roles · median 69 d
How we counted: 1353 open Design Verification (Design Verification) roles from 98 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.