Staff Engineer – DFT Engineering

Originally posted 18 September 2026 by the employer — open 0 days.

About the role

This role involves designing and implementing Design for Testability (DFT) features for complex integrated circuits within a VLSI design team. The position focuses on ensuring efficient and effective testability through various DFT techniques like LBIST, ATPG, DFT DRC, MBIST, Boundary Scan, JTAG, and Analog/Phy DFT.

What you'll do

• Collaborate with Design, Architecture, Product Test Engineering, and Physical Design teams to ensure efficient integrated circuit testability.
• Design and implement DFT features, including scan chains, compression, and built-in self-test structures.
• Conduct DFT DRC checks in RTL/Netlist database for compliance with DFT guidelines.
• Generate manufacturing ATPG test patterns for stuck-at (SAF) and transition fault (TDF) models using on-chip test compression.
• Design (including repair) and verify MBIST using EDA tools.
• Validate DFT structures/patterns in RTL, Netlist with and without SDF.

What you'll need

• Bachelor's/Master's degree in Electrical/Electronic Engineering or a related field.
• 7-10 years of hands-on experience in DFT methodologies and techniques.
• Strong knowledge of LBIST, ATPG, DFT DRC, Scan compression, Low power DFT Techniques, MBIST, Boundary Scan, Analog DFT, JTAG Architecture, and DFT STA Constraint development.
• Hands-on experience with Cadence/Siemen's DFT EDA tools for Scan stitching, DRC, ATPG, Coverage improvement, MBIST, and Boundary Scan.
• Proficiency in scripting languages such as Perl, Tcl, and/or Python.
• Solid understanding of digital design fundamentals, RTL coding, Lint/CDC, Low Power Checks, and ASIC design flow.