Staff Engineer, DFT
Originally posted 2 November 2026 by the employer.
About the role
The Staff Engineer, DFT is responsible for scan insertion, boundary scan, MBIST, and ATPG for ultra-low power SoCs based on subthreshold operation using standard EDA tools.
What you'll do
- Develop and implement low-power DFT architecture and infrastructure.
- Execute scan insertion, boundary scan, MBIST, and ATPG for ultra-low power SoCs.
- Generate structural test vectors, analyze, and improve test coverage, test time, and test cost.
- Perform pre-layout and post-layout scan and MBIST simulations.
- Collaborate with designers on STA, physical, power, and logical issues related to DFT.
- Work with test engineers to bring up test vectors on silicon and support production test programs.
What you'll need
- BS or MS in ECE/EE with at least 8 years of experience in DFT implementation.
- Skilled in DFT structures including scan (Stuck-At, At-Speed, Path-Delay), scan compression, boundary scan, and MBIST.
- Experience creating and implementing hierarchical DFT architecture in complex SoCs.
- Experience in low-power DFT, MBIST, and test time/coverage analysis for scan and MBIST patterns.
- Experience developing scan ATPG and MBIST testbenches and simulations in pre/post-layout environments.
- Hands-on experience with RTL and extensive knowledge of timing concepts and constraint development.
Nice to have
- Experience in scripting languages such as Tcl.
- Experience with GLS (gate level simulation).
More semiconductor jobs: DFT engineer jobs · Austin jobs
This role has been open 0 days — well below the 59-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
252
|
Median days open
59 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Ambiq Micro | All employers we track in this specialty (252 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 252 |
| Open roles in the wider Digital Design & Verification family | 14 | 3369 · 114 employers |
| Median days open | 32 d | 59 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Who's hiring in this category
- AMD · 36 open roles · median 54 d
- NVIDIA · 22 open roles · median 55 d
- Qualcomm · 22 open roles · median 81 d
- NXP Semiconductors · 19 open roles · median 46 d
- Synopsys · 18 open roles · median 33 d
- Intel Corporation · 9 open roles · median 62 d
How we counted: 252 open DFT Engineering (DFT Test) roles from 54 employers tracked in the SemiconductorJobs index, counted 2 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.