Staff Engineer, Design - Hyderabad - Phoenix Aquila, India

Originally posted 24 September 2026 by the employer.

Join the Non-Volatile Memory Datapath Functional Group.

About the role

This role involves supporting design and validation activities of Datapath and DDR high-speed interfaces for Flash Memory products, specifically focusing on the Non-Volatile Memory Datapath Functional Group.

What you'll do

• Support design and validation activities of Datapath and DDR high-speed interfaces of Flash Memory products.
• Engage in high-speed circuits block level and sub-system level design and timing optimization.
• Supervise complex analog layouts and define IP floorplans.
• Document block level and sub-system level Micro-Architecture Spec (MAS).
• Conduct high-speed circuits functional and timing validation using simulation tools.
• Bridge process technology, device modeling, circuit design, and architecture exploration for Design-Technology Co-Optimization (DTCO).

What you'll need

• Circuit design experience in analog/mixed signal CMOS circuits in deep sub-micron technologies (5 – 40 nm) in High-speed Memory interfaces (DDR3/4/5, LPDDR3/4x/5, GDDR5/6) or SerDes.
• Capability to define and execute integrated Analog/Mixed-Signal (AMS) solutions by combining circuit/analog and digital/RTL design techniques.
• Deep knowledge of high-speed digital, analog, and mixed-signal circuit design, including power delivery circuits such as Bandgap References, LDOs, Bias Circuits.
• Strong understanding of CMOS device physics, deep-submicron design challenges, power consumption trade-offs, mismatch analysis, Monte Carlo methodologies, transistor-level noise analysis, and circuit reliability considerations.
• Experience supervising complex analog layouts, defining IP floorplans, and driving parasitic-aware design methodologies through layout signoff.
• Proficiency with industry-standard EDA tools and design flows, including Cadence ADE/Virtuoso, Spectre, AMS Verification, EM/IR analysis, MATLAB, Calibre, and mixed-signal verification environments.
• Working knowledge of mixed-mode simulation, signal integrity, package interactions, ESD design, and system-level validation methodologies.
• Knowledge of digital design methodologies using RTL, with the ability to develop behavioral and system-level models using Verilog-A, Verilog/SystemVerilog, and Python.
• M.Tech. or Ph.D. in Microelectronics, or a related discipline, with 5+ years of semiconductor industry experience in analog/mixed-signal, high-speed interface, memory, SerDes, or AMS architecture design.

Nice to have

• Prior experience in Plane Datapath Design.
• Exposure to AI-Enabled, and Agentic AI technologies, with the ability to adopt a "Design + AI" approach.

Skills: Flash Memory, Datapath, DDR high-speed interfaces, analog/mixed signal CMOS, HSPICE