Staff Digital Verification Engineer
$160,000 - $210,000 USD yearly
Originally posted 1 September 2026 by the employer.
This role focuses on the functional verification of the Electron E1 processor.
About the role
This Staff Digital Verification Engineer will drive the functional verification of complex SoC/IP designs from specification through tapeout on a newly formed verification team, with a focus on the Electron E1 processor.
What you'll do
- Drive functional verification of complex SoC/IP designs.
- Architect UVM-based testbenches and constrained-random verification environments.
- Drive functional and code coverage to tapeout sign-off.
- Debug complex simulation failures.
- Communicate verification risk, status, and tradeoffs.
What you'll need
- 10+ years of progressive experience in ASIC/SoC design verification with multiple full cycles of ownership from testbench architecture through tapeout.
- Expertise in UVM-based testbench architecture and constrained-random verification methodology.
- C/C++ experience for modelling or verification.
- Demonstrated track record of driving functional and code coverage to tapeout sign-off on complex, multi-million-gate SoC/ASIC designs.
- Proven ability to debug complex simulation failures.
- Proficiency in Python for test automation, log analysis, coverage post-processing, and regression flow development.
Nice to have
- Experience in Formal verification (JasperGold or similar).
- Experience building or using AI Agentic flows for DV.
- Software/Firmware based testing experience and working with software teams pre-silicon.
- Post-silicon experience.
- Understanding and experience in processors (ARM, RISC-V), interconnects (AMBA AXI/ACE/CHI), memory controllers, DMA engines, interrupt controllers, and standard peripherals.
- Power aware verification and UPF.
Skills: ASIC/SoC design verification, UVM-based testbench, constrained-random verification, coverage closure, Python for test automation
This role has been open 43 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1187
|
Median days open
64 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Efficient Computer | All employers we track in this specialty (1187 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 1187 |
| Open roles in the wider Digital Design & Verification family | 6 | 3192 · 115 employers |
| Median days open | 43 d | 64 d (−21 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: ASIC/SoC design verification, UVM-based testbench, constrained-random verification, coverage closure, Python for test automation
Who's hiring in this category
- Qualcomm · 103 open roles · median 42 d
- AMD · 99 open roles · median 54 d
- NVIDIA · 79 open roles · median 61 d
- Synopsys · 61 open roles · median 30 d
- SiFive · 54 open roles · median 71 d
- Cadence Design Systems · 51 open roles · median 113 d
How we counted: 1187 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 14 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.