Design Verification Engineer, Amazon Leo - Austin, Texas, United States
Originally posted 28 August 2026 by the employer.
Amazon Leo is Amazon’s low Earth orbit satellite network.
About the role
This role involves defining and implementing digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways, focusing on modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies.
What you'll do
- Develop detailed test plans and write tests.
- Run regressions and collect coverage matrices.
- Debug system-level communication scenarios on pre-silicon and post-silicon environments.
- Participate in system-level verification using test benches constructed with UVM, SystemC, and DPI-C.
- Develop a highly automated environment to triage regression failures and report issues.
What you'll need
- Experience in defining and implementing digital chip SOCs for communications.
- Expertise in modems, high-speed interfaces, embedded processors, and DSP solutions.
- Proficiency with UVM, SystemC, and DPI-C for test bench construction.
- Ability to develop detailed test plans.
- Experience with regressions and coverage collection.
Skills: UVM, SystemVerilog, test plans, regressions, coverage
This role has been open 47 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1192 |
| Open roles in the wider Digital Design & Verification family | 28 | 3192 · 115 employers |
| Median days open | 28 d | 65 d (−37 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM, SystemVerilog, test plans, regressions, coverage
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.