Staff Digital Design Engineer – SOC Low Power, Clocking & Integration - Austin, United States
$143,150 - $265,850 USD monthly
Originally posted 9 June 2026 by the employer.
Design low-power clocking architectures and custom RISC-V infrastructure for Wireless MCU SoCs.
About the role
As a Staff Digital Design Engineer, you will develop integrated, low-power System on a Chip devices to serve the IoT wireless market. The team focuses on Wireless MCU SoCs featuring custom RISC-V cores and AI/ML components.
What you'll do
- Define and implement SoC-level low-power architecture, including power domains, retention, isolation, level shifters, power sequencing, and UPF/CPF-based power intent. - Design and integrate clocking infrastructure and reset architectures, including clock generation, distribution, gating, muxing, monitoring mechanisms, CDC, and RDC. - Drive RTL design and integration of infrastructure IPs such as power management controllers, clock controllers, reset controllers, DMA engines, and bus fabrics. - Architect and integrate SoC interconnects and on-chip bus fabrics including AXI, AHB, and APB to connect processors, memories, peripherals, and third-party IPs. - Lead small teams of design engineers to architect, design, and verify digital subsystems. - Analyze and debug integration, low-power, and clocking issues during simulation, emulation, synthesis, and silicon bring-up.
What you'll need
- BS or MS in Electrical Engineering with 10 to 20 years of professional experience in digital CMOS IC design. - RTL design expertise using Verilog and SystemVerilog. - Experience with low-power design methodologies, including UPF, power gating, retention, isolation, level shifting, and power-aware verification. - Understanding of SoC clocking architectures, clock domain crossing (CDC), reset domain crossing (RDC), synchronization techniques, and timing considerations. - Experience with on-chip bus protocols including AXI, AHB, and APB, as well as integrating processor clusters, memory subsystems, and third-party IPs. - Experience with logic simulators, gate-level simulation, logic synthesis, timing constraints, and scripting using Python, Perl, or Tcl.
This role has been open 135 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1084
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Silicon Labs | All employers we track in this specialty (1084 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1084 |
| Open roles in the wider Digital Design & Verification family | 20 | 3322 · 115 employers |
| Median days open | 49 d | 63 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 160 open roles · median 60 d
- Synopsys · 87 open roles · median 36 d
- AMD · 77 open roles · median 42 d
- Analog Devices · 49 open roles · median 53 d
- NXP Semiconductors · 42 open roles · median 92 d
- NVIDIA · 39 open roles · median 64 d
How we counted: 1084 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.