Staff Digital Design Engineer, HBM - Richardson, TX, United States

Originally posted 25 June 2026 by the employer.

Micron Technology is seeking a Staff Digital Design Engineer to contribute to the architecture, RTL development, verification, and delivery of high‑performance digital logic blocks for advanced HBM memory products.

About the role

This role involves contributing to the architecture, RTL development, verification, and delivery of high‑performance digital logic blocks for advanced HBM memory products within the HIG HBM Digital Design Group.

What you'll do

• Drive all stages of the digital design flow, including concept definition, specification, RTL implementation, verification support, documentation, and post‑silicon debug.
• Develop high‑quality RTL in Verilog/SystemVerilog using scalable, parameterized design techniques aligned to architectural specifications.
• Define and refine micro‑architecture for digital logic blocks, including FSMs, datapath, FIFOs, pipelines, and arbitration logic.
• Analyze tradeoffs across area, power, latency, and throughput, providing clear documentation and communication of design decisions.
• Perform CDC/RDC analysis, apply sound clocking and reset strategies, and identify early timing challenges.
• Support synthesis and static timing analysis by crafting and debugging SDC constraints, and interpreting timing reports.
• Apply low‑power design methodologies including CPF/UPF, clock gating, multi‑domain partitioning, and isolation/level shifter strategies.
• Collaborate with verification, DFT, physical design, and CAD teams to ensure robust design closure and high coverage, including scan/ATPG readiness and functional/formal verification support.

What you'll need

• Bachelor’s degree or equivalent experience in Electrical Engineering with strong understanding of computer architecture (3–5 years proven experience).
• Sophisticated RTL design proficiency using Verilog/SystemVerilog with experience translating specifications into maintainable micro‑architecture and RTL.
• Solid grasp of digital logic fundamentals including FSMs, pipelines, datapath/control partitioning, and buffering/flow control structures.
• Experience with synthesis, STA, investigating CDC/RDC issues, and creating timing constraints.
• Proficiency in Linux environments with scripting skills (Python and/or Perl) to automate design flows and improve productivity.

Nice to have

• Master’s degree in Electrical/Computer Engineering with 5–10 years of related experience.
• Knowledge of memory system concepts (DRAM/SRAM/eFuse), ECC/CRC techniques, DFT methodologies including memory/logic BIST.
• Experience with AMBA/AXI/APB or comparable bus protocols, and working with custom or third‑party macros using behavioral and timing models.