Staff DFx Methodology Architect - CA, San Jose, United States
$145,600 - $249,600 USD yearly
Originally posted 9 June 2026 by the employer.
About the role
The AECG organization at AMD is seeking a DFx Architecture, Methodology and Logic Design Expert with strengths in RTL and Timing to support FPGA-SoCs and custom ASICs. You will own and drive DFx Architecture definition, RTL implementation, and methodology development.
What you'll do
- Define and lead SoC-DFx Architecture, Specifications, and development of DFx-IPs. - Own DFx Architecture documentation, accounting for interactions with hardware and firmware. - Implement DFx features in RTL using Verilog and SystemVerilog. - Co-own Timing and Design Quality Checks and waivers for DFx-IPs. - Work cross-functionally with execution and verification teams to enable integration and validation across design implementation phases. - Engage with validation and product teams on test plans, coverage, silicon bring up, and silicon debug.
What you'll need
- Bachelor's, Master's, or PhD degree in Computer or Electrical Engineering. - Hands-on experience driving Architecture, Design Methodologies, RTL, and Timing through tapeout and production. - Expertise in RTL implementation using Verilog and SystemVerilog. - Experience with timing and design quality checks for IP blocks.
Nice to have
- Proficiency with Siemens Tessent DFT flows, including Tessent Shell, Tessent Scan, Tessent ATPG, Tessent MemoryBist, IJTAG, and SSN. - Understanding of 1149.1 and 1687 standards, ATPG concepts, and experience in 2.5D and 3D IC testing. - Strong understanding of DFT Architecture and Debug methodologies. - Strong foundation in logic design, switching theory, and timing. - Experience supporting silicon debug and diagnosis. - Scripting experience with Perl, Python, and TCL.
Skills: DFx Architecture, Tessent DFT, ATPG, Scan Chain, IJTAG
This role has been open 135 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 248 |
| Open roles in the wider Digital Design & Verification family | 255 | 3322 · 115 employers |
| Median days open | 44 d | 63 d (−19 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: DFx Architecture, Tessent DFT, ATPG, Scan Chain, IJTAG
Who's hiring in this category
- AMD (this employer) · 38 open roles · median 45 d
- Qualcomm · 26 open roles · median 73 d
- NVIDIA · 23 open roles · median 42 d
- NXP Semiconductors · 19 open roles · median 47 d
- Synopsys · 15 open roles · median 30 d
- Intel Corporation · 11 open roles · median 53 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 24 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.