Staff Design Verification Engineer – SoC and eFPGA - CA, San Jose, Rio Robles, United States
$150,978 - $218,624 USD yearly
Originally posted 6 August 2026 by the employer.
Help develop eFPGA technology and the SoCs that integrate it.
About the role
As a Staff Design Verification Engineer, you will contribute to the development of eFPGA technology and the SoCs that integrate it. This role involves verifying complex subsystems to ensure the successful delivery of high-quality silicon products.
What you'll do
- Partner with architecture, RTL, firmware, and software teams to understand new features and define comprehensive verification strategies.
- Develop detailed verification plans covering feature interactions, system-level behavior, and hardware/software use cases.
- Design, implement, and maintain directed and constrained-random verification environments and test suites.
- Develop SystemVerilog assertions and functional coverage models to ensure thorough verification.
- Debug simulation failures, identify root causes, and collaborate with design and firmware engineers to resolve issues.
- Analyze functional and code coverage metrics and enhance verification content to achieve coverage goals.
- Build and support end-to-end verification flows for eFPGA soft logic within SoCs, including RTL simulation, synthesis validation, and bitstream generation.
What you'll need
- Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent industry experience.
- Strong understanding of SoC architectures and industry-standard bus protocols such as AXI and AHB.
- Experience debugging RTL and firmware using simulation and waveform analysis tools.
- Hands-on experience developing UVM-based verification environments.
- Proficiency in SystemVerilog, Verilog, C/C++, and Python.
- Experience developing automation solutions and working within distributed compute environments.
- Working knowledge of SystemC and Transaction-Level Modeling (TLM).
- Solid understanding of digital design fundamentals, computer architecture, timing analysis, power analysis, process variation, and reliability considerations.
Nice to have
- 5+ years of experience in SoC, subsystem, or microarchitecture verification.
- Experience supporting successful silicon tape-outs in advanced process nodes (N4, N5 or similar technologies).
- Knowledge of Functional Safety (FuSA) requirements and safety-focused hardware verification methodologies.
- Experience with FPGA or programmable logic architectures.
- Familiarity with continuous integration, regression automation, and verification productivity tools.
Skills: UVM, SystemVerilog, functional coverage, eFPGA, SoC architectures
This role has been open 73 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Analog Devices | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 36 | 1202 |
| Open roles in the wider Digital Design & Verification family | 92 | 3201 · 115 employers |
| Median days open | 64 d | 65 d (−1 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: UVM, SystemVerilog, functional coverage, eFPGA, SoC architectures
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.