Digital and Mixed Signal IC Design/DV Engineer - Tucson, AZ, United States
Originally posted 7 August 2026 by the employer.
Join our dynamic Current Sensing product line developing Shunt and Hall based mixed signal current sensing ICs.
About the role
This role involves comprehensive IC development, design, and verification for mixed-signal current sensing ICs. You will contribute to the Current Sensing product line that develops Shunt and Hall based mixed signal current sensing ICs.
What you'll do
- Contribute to the full IC development lifecycle, including RTL design, synthesis, place and route, scan pattern generation, and timing analysis.
- Develop and implement robust, scalable verification methodologies for mixed-signal ICs, including testbench creation and automation using DMS and AMS stimulus and checkers.
- Create comprehensive test plans, tests, and simulations at RTL and gate levels using SystemVerilog (SV), VHDL, and the UVM environments.
- Work closely with design and system teams to define Design for Verification (DFV) architectures, triage and resolve bugs.
- Drive verification coverage to meet defined goals, track progress, and communicate status, issues, and risks effectively.
- Develop and contribute to the evolution of our DV strategy, tools, scripts and methodologies to improve quality, efficiency and automation.
What you'll need
- Atleast 2 years of relevant experience
- A thorough understanding of digital logic design
- Familiarity with the Verilog, System Verilog, VHDL language and simulators
- Ability to solve problems using a systematic approach
Nice to have
- A good understanding of analog functionality and exposure to analog IC design methods.
- Understanding and knowledge of analog and digital design principles, including RTL, FSMs, GLS, timing, synchronization, and power domains, mixed-signal and digital verification flow and analog block modeling.
- Experience with timing verification using Gates+SDF, electrical PVT variation, and timing analysis across analog/digital boundaries
Skills: mixed-signal ICs, verification methodologies, testbench creation, SystemVerilog (SV), UVM environments, RTL design
This role has been open 71 days — slightly above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1202
|
Median days open
65 d
|
Median salary
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Texas Instruments | All employers we track in this specialty (1202 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 28 | 1202 |
| Open roles in the wider Digital Design & Verification family | 77 | 3202 · 115 employers |
| Median days open | 35 d | 65 d (−30 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: mixed-signal ICs, verification methodologies, testbench creation, SystemVerilog (SV), UVM environments, RTL design
Who's hiring in this category
- Qualcomm · 110 open roles · median 39 d
- AMD · 96 open roles · median 51 d
- NVIDIA · 84 open roles · median 59 d
- Synopsys · 64 open roles · median 33 d
- SiFive · 55 open roles · median 75 d
- Cadence Design Systems · 50 open roles · median 117 d
How we counted: 1202 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 18 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.