Staff Design Verification Engineer - Bangalore, Karnataka, India
Originally posted 29 September 2026 by the employer.
About the role
This role involves ensuring the functional correctness, robustness, and quality of semiconductor and SoC designs.
What you'll do
- Develop and execute comprehensive verification plans.
- Close verification with coverage closure.
- Create and enhance testbenches using SystemVerilog (OVM/UVM).
- Implement reusable Verification IP (VIP) components.
- Apply constraint random verification methodology.
- Collaborate with internal teams and external customers.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
- 10 Years of experience in SoC/IP verification.
- Strong expertise in SystemVerilog, UVM, and advanced verification methodologies.
- Hands-on experience with ARM-based SoC architectures, AMBA protocols (AXI/AHB/APB), and system-level interactions.
- Proven ability to build reusable, scalable testbench architectures.
- Solid understanding of test planning, coverage-driven verification, and verification metrics.
- Experience with GLS, timing verification, and debug.
- Knowledge of power-aware verification (UPF/CPF).
- Strong scripting and automation skills (Python, Perl, Shell, Make, etc.).
- Exposure to AI/ML techniques applied to verification (e.g., intelligent stimulus generation, failure triage, coverage optimization).
Nice to have
- Experience with low-power verification using UPF (Unified Power Format).
- Knowledge of formal verification techniques.
Skills: SystemVerilog, UVM, verification plans, testbench, functional coverage
This role has been open 1 day — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1185
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | onsemi | All employers we track in this specialty (1185 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 15 | 1185 |
| Open roles in the wider Digital Design & Verification family | 56 | 3105 · 115 employers |
| Median days open | 60 d | 63 d (−3 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: SystemVerilog, UVM, verification plans, testbench, functional coverage
Who's hiring in this category
- AMD · 102 open roles · median 40 d
- Qualcomm · 99 open roles · median 54 d
- NVIDIA · 88 open roles · median 70 d
- Synopsys · 63 open roles · median 22 d
- SiFive · 57 open roles · median 57 d
- NXP Semiconductors · 52 open roles · median 77 d
How we counted: 1185 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.