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QORVO

Staff CAD Engineer - Newbury Park, CA, United States

QORVO Newbury Park, CA, US, 91320, United States 21 days ago
Digital Design & SoC Architecture

$125,400 - $163,000 USD yearly

Originally posted 14 September 2026 by the employer — open 0 days.

About the role

This Staff CAD Engineer role focuses on PCB design and fabrication for high performance RF and power product lines.

What you'll do

  • Execute end-to-end PCB design, including schematic capture and complex PCB layout, from concept to fabrication, assembly, and production builds using Altium or Cadence tools.
  • Set standards, design rules, and IPC compliance practices for high frequency PCB designs and fabrication documentation.
  • Lead root cause investigation and corrective action for design/fabrication issues involving IPC standards, signal integrity, thermal, and mechanical interactions.
  • Perform pre and post layout SI/PI/EM analysis using Cadence Sigrity or equivalent tools.
  • Develop transmission line models, impedance controlled routing, crosstalk, and PDN analysis, driving simulation-based optimization for DDR4/DDR5, PCIe, SerDes, Ethernet, USB, and RF interfaces.
  • Apply DFx methodologies (DFM, DFA, DFT, DFR) and HDI techniques for manufacturability, testability, reliability, and high pin count BGA routing.

What you'll need

  • 15+ years of combined experience in PCB/PWB design, CAD layout, and/or fabrication/supplier development, with IPC certification(s).
  • Deep proficiency with ECAD/mechanical CAD tools: Altium, Cadence Allegro, ADS, AutoCAD, SolidWorks, and CAM350.
  • Extensive knowledge of PCB/PWB manufacturing processes, materials, and IPC standards, with proven application of GD&T and DFM/DFA/DFT/DFR principles.
  • Strong RF/high frequency design background, including high frequency laminates and applications such as ATE multisite load boards and probe cards.
  • Hands-on experience with Cadence Sigrity or equivalent program and related SI/PI/EM simulation environments.
  • Strong understanding of transmission line theory, impedance control, signal propagation, reflection, crosstalk, termination methods, PDN, and grounding.
  • Experience with pre and post layout SI/PI analysis for DDR4/DDR5, PCIe, Ethernet, USB, SerDes, and high-speed ATE applications.

Skills: PCB design, Altium, Cadence Allegro, SI/PI/EM analysis, high frequency PCB, DDR4/DDR5, PCIe, SerDes

Market context

This role has been open 0 days — well below the 118-day median for Hardware Systems Engineering roles.

Hardware Systems Engineering · Serdes Highspeed

Open roles in category
89
Median days open
118 d
Median salary
$197k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How QORVO compares in Hardware Systems Engineering hiring
Metric QORVO All employers we track in this specialty (89 roles · 32 employers)
Open roles in this specialty 1 89
Open roles in the wider Software, Firmware & Systems family 27 5687 · 145 employers
Median days open 0 d 118 d (−118 d vs this employer)
Median salary (USD postings) — $197k

Skills observed across this category: PCB design, Altium, Cadence Allegro, SI/PI/EM analysis, high frequency PCB, DDR4/DDR5, PCIe, SerDes

Who's hiring in this category

  • NVIDIA · 12 open roles · median 158 d
  • Qualcomm · 12 open roles · median 158 d
  • AMD · 9 open roles · median 77 d
  • Keysight Technologies · 7 open roles · median 107 d
  • Marvell Technology · 6 open roles · median 168 d
  • Etched · 4 open roles · median 160 d

How we counted: 89 open Hardware Systems Engineering (Serdes Highspeed) roles from 32 employers tracked in the SemiconductorJobs index, counted 14 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Software, Firmware & Systems family row. Figures refresh nightly.

Apply now
Newbury Park, CA, US, 91320, United States
On-site
$125,400 - $163,000 USD yearly
21 days ago

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