Staff Analog IC Layout Engineer (Block & Chip) - San Diego, California, United States

Originally posted 3 September 2026 by the employer.

About the role

As a Staff Analog Layout Engineer, you will take technical ownership of the physical layout and verification of complex analog and mixed-signal integrated circuits for the ATE market. This role involves working with advanced process technologies ranging from 65nm CMOS to 100+V BCD.

What you'll do

• Perform physical layout of analog and mixed-signal integrated circuits at both the block and full-chip level.
• Develop floorplans and optimize component placement for area, performance, and power.
• Perform LVS and DRC verification to ensure layout accuracy and compliance with process design rules.
• Collaborate with design engineers to translate circuit requirements into high-quality physical layouts.
• Partner with digital design, packaging, and other cross-functional teams to optimize overall chip performance.
• Troubleshoot and resolve layout, verification, and manufacturability issues.

What you'll need

• Bachelor’s degree in Electrical Engineering or a related field.
• Minimum of 8 years of professional experience in analog and mixed-signal IC layout design.
• Strong understanding of analog CMOS circuits and device physics.
• Solid knowledge of the IC design, qualification, and manufacturing lifecycle.
• Hands-on experience with industry-standard EDA tools such as Cadence, Mentor Graphics, or Tanner.
• Proficiency in LVS and DRC verification using Cadence or Mentor tools.

Skills: physical layout, analog and mixed-signal ICs, floorplans, LVS and DRC verification, Cadence EDA tools