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Synopsys

SRAM Design Engineer, Staff

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Hsinchu, Taiwan 4 months ago
Digital Design & SoC Architecture

Originally posted 17 June 2026 by the employer. Relisted by the employer on 17 August 2026.

About the role

This role involves designing, verifying, and characterizing SRAM integrated circuits and developing SRAM compilers. The focus includes SRAM bitcell analysis and integrating SP/2P/ROM variety designs into SRAM IP solutions.

What you'll do

  • Design and verify SRAM integrated circuits to ensure robustness and reliability.
  • Develop SRAM compilers, including gds and netlist tiling.
  • Characterize SRAM timing, power, and other critical metrics.
  • Conduct SRAM bitcell analysis and formulate design criteria.
  • Utilize EDA tools (XA, hspice, Verilog, Starrc, EMIR) for simulation, verification, and design optimization.
  • Collaborate with cross-functional teams to address post-silicon debug and implement improvements.

What you'll need

  • Master's degree in Electrical/Electronic Engineering or a related field.
  • 3–7+ years of hands-on experience in SRAM circuit design.
  • Prior understanding of CMOS-based block level circuit design and SRAM architectures.
  • Experience with SP/2P/ROM variety design and SRAM bitcell analysis.
  • Proficiency in digital circuit design and VLSI process concepts.
  • Familiarity with scripting languages such as Python, Tcl/Tk, Perl, and Unix shell.
  • Experience with EDA tools for simulation and design: XA, hspice, Verilog, Starrc, EMIR.

Nice to have

  • Post-silicon debug experience is a plus.

Skills: SRAM circuit design, SRAM compilers, bitcell analysis, CMOS circuit design, EDA tools

Market context

This role has been open 109 days — well above the 69-day median for Memory Design roles.

Memory Design · Memory Design

Open roles in category
287
Median days open
69 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Memory Design hiring
Metric Synopsys All employers we track in this specialty (287 roles · 29 employers)
Open roles in this specialty 27 287
Median days open 49 d 69 d (−20 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: SRAM circuit design, SRAM compilers, bitcell analysis, CMOS circuit design, EDA tools

Who's hiring in this category

  • Micron Technology · 151 open roles · median 86 d
  • Synopsys (this employer) · 27 open roles · median 49 d
  • SanDisk · 17 open roles · median 32 d
  • Broadcom · 16 open roles · median 50 d
  • Qualcomm · 12 open roles · median 149 d
  • NVIDIA · 7 open roles · median 59 d

How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Hsinchu, Taiwan
On-site
4 months ago

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