Sr. Staff SoC Power & Performance Architect - Austin, Texas, United States
Originally posted 21 August 2026 by the employer — open 26 days.
About the role
This role is for a Sr. Staff Power & Performance Architect to drive power and performance analysis, budgeting, modeling, and debug from early architecture through silicon correlation.
What you'll do
- Execute power and performance analysis across pre-silicon modeling, RTL power analysis, power-aware simulation, and post-silicon correlation.
- Build and maintain SoC, subsystem, and use-case-level power budgets.
- Drive variance analysis against power and performance targets.
- Lead architectural debug of power anomalies in simulation, emulation, or silicon.
- Develop and automate power modeling infrastructure, reporting flows, regression dashboards, and analysis tooling using Python and/or TCL.
- Characterize power states, transitions, leakage/dynamic splits, Vmin behavior, retention, and corner behavior on first silicon.
What you'll need
- BS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 7+ years of architecture experience in low-power SoC, embedded SoC, semiconductor, MCU, processor, or related silicon environments.
- Hands-on ownership of power and/or performance analysis, budgeting, and debug.
- Experience with Cadence Genus or equivalent industry power analysis tooling (Cadence Joules, Synopsys PrimePower, Siemens PowerPro).
- Experience with power-aware simulation flows.
- Strong Python and/or TCL scripting for modeling, automation, reporting, and analysis.
- Demonstrated ability to write architecture and microarchitecture specifications.
- Ability to work effectively across hardware, software, physical design, validation, applications, field, marketing, and sales teams.
- Experience with collaboration tools such as Confluence, SharePoint, JIRA, and Git.
Nice to have
- MS or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 10+ years of semiconductor or embedded SoC industry experience.
- UPF / IEEE 1801 authoring or review experience.
- Clocking/reset architecture experience.
- Arm Cortex-M architecture experience.
- Experience with Arm Cortex-A, RISC-V, DSP, or heterogeneous multicore architectures.
- Experience with APB, AHB, AXI, NoC, cache, pseudo-SRAM, DRAM, non-volatile memory, or high-bandwidth memory topologies.
- Prior customer-facing, pre-sales, field, or applications engineering engagement.
- Familiarity with AI-assisted engineering environments such as Claude Code, Cursor, or equivalent.
Skills: SoC Power & Performance Architect, energy efficiency, sub- and near-threshold technology, AI edge revolution
This role has been open 26 days — well below the 65-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
447
|
Median days open
65 d
|
Median salary
$244k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Ambiq Micro | All employers we track in this specialty (447 roles · 62 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 447 |
| Open roles in the wider Digital Design & Verification family | 12 | 3007 · 114 employers |
| Median days open | 39 d | 65 d (−26 d vs this employer) |
| Median salary (USD postings) | — | $244k |
Skills observed across this category: SoC Power & Performance Architect, energy efficiency, sub- and near-threshold technology, AI edge revolution
Who's hiring in this category
- Qualcomm · 67 open roles · median 76 d
- NVIDIA · 56 open roles · median 50 d
- AMD · 33 open roles · median 69 d
- Arm Holdings · 27 open roles · median 84 d
- Renesas Electronics · 23 open roles · median 42 d
- Apple · 19 open roles · median 8 d
How we counted: 447 open SoC/Chip Architecture (SOC Architecture) roles from 62 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.