Sr. Staff/Principal Engineer - Low Power Chip Architect / System Engineer

Originally posted 2 June 2026 by the employer.

About the role

This role is responsible for defining the architecture, driving transistor-level design, and enabling system-level integration of ultra-low-power integrated circuits (ICs) for Robotics and Industrial IoT (IIoT) applications. You will bridge high-performance Analog Front Ends (AFEs) with digital logic and firmware, leading programs from initial architecture and specification through simulation, verification, tape-out, and early silicon bring-up onsite in San Diego.

What you'll do

- Define and support end-to-end system architecture, including partitioning across analog, digital, firmware, and system domains, while balancing power, performance, noise, latency, and silicon area. - Lead feasibility studies and transistor-level design of mixed-signal building blocks including ADCs, DACs, PLLs/DLLs, LDOs, and SerDes. - Architect and integrate ultra-low-power AFEs optimized for battery-operated IIoT and Robotics sensor ASICs, collaborating with internal teams, third-party IP vendors, and design houses. - Develop behavioral and system-level models using MATLAB/Simulink (or equivalent tools) to evaluate noise, linearity, and SNR. - Perform pre-silicon verification across PVT corners using industry-standard simulators and support post-silicon bring-up, characterization, and reliability qualification (including HTOL and burn-in). - Support multi-modal sensor data acquisition, sensor fusion, edge AI inference workflows, and hardware–software integration.

What you'll need

- Bachelor's degree in Science, Engineering, or related field with 8+ years, Master's degree with 7+ years, or PhD with 6+ years of ASIC design, verification, validation, integration, or related work experience. - Experience defining system architecture and partitioning across analog, digital, and firmware domains. - Direct background in transistor-level mixed-signal design and integration. - Ability to work onsite in San Diego 5 days a week.

Nice to have

- Ph.D. in Electrical Engineering (or related field) with 8 years, or M.S. with 10–12 years of post-degree industrial IC/system design experience. - Strong expertise in low-power analog and mixed-signal (AMS) IC design, along with hands-on experience using Cadence Virtuoso, AMS sims, Verilog, Spectre, HSPICE, and board-level simulation methodologies. - Solid understanding of PDKs, LVS, DRC, PEX flows, and experience with ESD and reliability standards (HBM, CDM, TLP). - Experience as a Chip Lead, System Architect, or Technical Lead driving silicon programs from concept to production. - Experience with digital design flows (synthesis and timing analysis), firmware development, scripting in Python, and embedded interfaces such as I2C, I3C, SPI, and MIPI. - Experience with deep submicron CMOS technologies, low-power fabrication processes, IC packaging, board-level validation, and sensor systems/edge AI applications.

Skills: system architecture, mixed-signal building blocks, ADCs, DACs, PLLs/DLLs, LDOs, SerDes, low-power analog