Sr. Staff Power Performance Architect - Santa Clara, United States
Originally posted 9 April 2026 by the employer.
About the role
d-Matrix is looking for a Senior Staff Power Performance Architect to own pre-silicon power estimation across AI accelerators. The role drives RTL-level and physical-design-level power estimation while building an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads.
What you'll do
- Own pre-silicon power estimation for design blocks, spanning both RTL-level and physical-design-level estimation. - Partner with front-end and DV engineers to identify power activity windows, and work with the RTL team to implement estimation feedback and optimize power. - Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts of compute/memory blocks. - Collaborate with frontend architects and backend design to define performance monitor availability, system requirements, and usage, then drive that analysis into hardware capability improvements and die-level design modifications. - Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification. - Design and implement performance-enabling and power-saving/monitoring functions, and participate in silicon bring-up and validation.
What you'll need
- 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design, with a Master's degree in Electrical Engineering, Computer Engineering, or Computer Science. - Understanding of power, performance, micro-architecture, RTL, and physical design across the full IC design flow (Arch → uarch → RTL → Schematic → Layout → Verification → Fabrication → HVM). - Familiarity with at least one EDA tool for power estimation. - Experience building script utilities to improve design execution productivity across RTL and physical design. - Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking.
Nice to have
- Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average. - Familiarity with power/frequency scaling techniques including DFS, DVFS, AFS, and AVFS. - Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis.
Skills: pre-silicon power estimation, RTL power estimation, architectural power estimation tool, micro-architecture, AI workloads
This role has been open 129 days — well above the 77-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
473
|
Median days open
77 d
|
Median salary
$238k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | d-Matrix | All employers we track in this specialty (473 roles · 67 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 473 |
| Open roles in the wider Digital Design & Verification family | 3 | 3322 · 115 employers |
| Median days open | 129 d | 77 d (+52 d vs this employer) |
| Median salary (USD postings) | — | $238k |
Skills observed across this category: pre-silicon power estimation, RTL power estimation, architectural power estimation tool, micro-architecture, AI workloads
Who's hiring in this category
- Qualcomm · 79 open roles · median 86 d
- NVIDIA · 53 open roles · median 72 d
- Apple · 37 open roles · median 15 d
- AMD · 35 open roles · median 72 d
- Arm Holdings · 27 open roles · median 120 d
- Micron Technology · 21 open roles · median 99 d
How we counted: 473 open SoC/Chip Architecture (SOC Architecture) roles from 67 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.