This role owns and drives physical design for multi-million-gate AMD graphics IP blocks.
Originally posted 9 November 2026 by the employer.
About the role
This role owns and drives physical design for multi-million-gate AMD graphics IP blocks targeting AI data center chips. Execution spans floorplanning, synthesis, and placement through clock tree synthesis, routing, timing closure, extraction, physical verification, and signoff.
What you'll do
- Own the physical design of complex, multi-million-gate graphics IP blocks to meet performance, power, and area targets.
- Partner with RTL design teams to identify frequency bottlenecks and resolve logic-level and timing issues.
- Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
- Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final signoff.
- Establish and improve physical design methodologies, design-quality checks, and automated scripting flows using Python and TCL.
- Provide technical leadership and mentorship to engineers across geographically distributed teams through design closure.
What you'll need
- Experience in physical design for high-performance semiconductor designs, including timing closure and physical signoff.
- Experience with synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control-logic applications.
- Experience with floorplanning, clock tree synthesis, clock and power gating, scan stitching, routing, extraction, and physical verification.
- Experience with physical design and signoff tools including Synopsys ICC2, ICC, Fusion Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedHawk, or Cadence Innovus and Genus.
- Proficiency with Python and TCL for design-flow development and automation.
- Bachelors or Masters degree in Electronics or Electrical Engineering.
Nice to have
- Experience with advanced process technologies, including N2P or below.
- Experience establishing design methodologies, integrating IP, performing logic-equivalence checks, and validating physical, timing, and electrical quality for large IP delivery.
- Experience applying or developing AI techniques for performance, power, and area optimization.
- Familiarity with RTL design, logic-level optimization, and computer organization/architecture.
Skills: place and route, timing closure, floorplanning, CTS, physical verification, signoff
More semiconductor jobs: AMD jobs · Physical design jobs · Texas jobs
This role has been open 0 days — well below the 60-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
716
|
Median days open
60 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | AMD | All employers we track in this specialty (716 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 62 | 716 |
| Open roles in the wider Physical Implementation family | 87 | 1609 · 116 employers |
| Median days open | 42 d | 60 d (−18 d vs this employer) |
| Median salary (USD postings) | — | $187k |
Skills observed across this category: place and route, timing closure, floorplanning, CTS, physical verification, signoff
Who's hiring in this category
- Qualcomm · 104 open roles · median 60 d
- AMD (this employer) · 62 open roles · median 41 d
- Broadcom · 47 open roles · median 20 d
- NVIDIA · 45 open roles · median 82 d
- Synopsys · 44 open roles · median 39 d
- Intel Corporation · 32 open roles · median 31 d
How we counted: 716 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 9 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Physical Implementation family row. Figures refresh nightly.