Sr/Staff Design Verification Engineer, HBM Verification Architecture - Richardson, TX, United States
Originally posted 21 April 2026 by the employer.
Develop verification architecture and testbenches for High Bandwidth Memory (HBM) DRAM products using TSV technology.
About the role
As a Senior Verification Engineer in the Heterogeneous Integration Group, you will contribute to modular, scalable verification solutions spanning IP-level and SoC-level verification for High Bandwidth Memory (HBM) DRAM products. The group develops HBM solutions using Through Silicon Via (TSV) technology across custom digital and RTL2GDS flows.
What you'll do
- Develop and implement verification plans and architecture collateral across IP-level and SoC-level verification for current and future HBM designs. - Support co-verification of the overall system and participate in customer interactions to gather feedback and provide recommendations for future HBM solutions. - Build and improve verification methodology components and GenAI applications aligned to HBM design cycles across custom digital and RTL2GDS flows. - Evaluate and debug pre-silicon and post-silicon issues in current HBM products, and contribute to the exploration of new HBM verification architectures.
What you'll need
- Bachelor's degree or higher in Electrical Engineering, Computer Engineering, or a related field. - 4+ years of relevant verification engineering experience, including over 3 years in digital (Verilog), analog (FastSpice), or mixed-signal verification (co-sims or real number modeling). - Over 2 years of experience working in custom design verification (schematic-based) or RTL design verification flows. - Ability to independently evaluate technical issues and define solutions.
Nice to have
- Master's in Electrical Engineering, Computer Engineering, or related field, or equivalent experience, accompanied by more than 3 years in verification engineering roles. - One or more patents, trade secrets, or publications in verification solutions. - Over 2 years in memory products using JEDEC specifications (preferably HBM), with experience building or improving verification flows.
Skills: HBM designs, IP-level verification, SoC-level verification, digital (Verilog), analog (FastSpice), mixed-signal verification
This role has been open 216 days — well above the 66-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1254
|
Median days open
66 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (1254 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 45 | 1254 |
| Open roles in the wider Digital Design & Verification family | 106 | 3346 · 116 employers |
| Median days open | 74 d | 66 d (+8 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: HBM designs, IP-level verification, SoC-level verification, digital (Verilog), analog (FastSpice), mixed-signal verification
Who's hiring in this category
- Qualcomm · 118 open roles · median 45 d
- AMD · 92 open roles · median 55 d
- NVIDIA · 91 open roles · median 65 d
- Synopsys · 65 open roles · median 41 d
- SiFive · 55 open roles · median 83 d
- Cadence Design Systems · 52 open roles · median 125 d
How we counted: 1254 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 26 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.