Sr. Staff Design Verification Engineer - CA, San Jose, United States

Originally posted 4 September 2026 by the employer.

This role supports IP development for Silicon implementation and first-time-right SW solution for Adaptive & Embedded Computing Group (AECG) device programs.

About the role

As a Sr. Staff Design Verification Engineer, you will be a key member of AMD’s FPGA Product and Platform development team, with responsibilities in the technical execution of Adaptive & Embedded Computing Group (AECG) device programs from definition to productization. This role supports IP development for Silicon implementation and first-time-right SW solution.

What you'll do

• Participate in all stages of the design flow, from RTL development through GDS implementation.
• Design and implement RTL for complex digital and mixed-signal blocks using Verilog and System Verilog.
• Support physical design activities, including synthesis, DFT implementation, place-and-route, and Static Timing Analysis (STA).
• Collaborate closely with Functional Verification teams to support block-level verification using constrained-random and directed test environments based on System Verilog and UVM.
• Utilize scripting languages such as Perl, Tcl, Shell, and Python to maintain existing design automation flows and develop new tools.
• Partner with cross-functional teams across multiple engineering disciplines and geographic locations.

What you'll need

• Strong understanding of the complete ASIC/SoC development flow, from RTL architecture through physical implementation and silicon bring-up.
• Strong RTL design and integration experience using Verilog and SystemVerilog.
• Experience working with high-speed interfaces and complex IPs such as HBM, Die-to-Die (D2D), SerDes, PCIe, and memory subsystems.
• Deep understanding of VLSI design principles, Design Automation methodologies, and IC development processes.
• Working knowledge of physical design concepts including floorplanning, synthesis, place-and-route, timing closure, and Static Timing Analysis (STA).
• Hands-on experience with industry-standard EDA tools such as Synopsys DFT Compiler, TestMAX, PrimeTime, VCS, and Cadence tool suites.
• Experience with UVM/OVM verification methodologies, testbench development, BFMs, simulation environments, and debug workflows.
• Proven experience implementing DFT solutions for large-scale SoCs, including scan, compression, MBIST, LBIST, boundary scan, and related test technologies.
• Strong scripting and automation skills using Perl, Tcl, Shell, Python, or similar languages.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

Nice to have

• Familiarity with FPGA architectures and prototyping methodologies.

Skills: DFT architecture, Scan insertion, ATPG, Mentor TestKompress, Synopsys Tetramax