Sr Staff CAD Engineer
Develop physical verification CAD flows and design rule decks utilizing Synopsys ICV and Mentor Calibre for SoC signoff.
Originally posted 11 November 2026 by the employer.
About the role
This role is part of Marvell Central Engineering, focusing on developing automated design flows and add-on tools. You will support physical verification, develop run sets, and build CAD flows from physical verification through SoC tapeout.
What you'll do
- Develop run sets for nanotechnology, support Calibre and Synopsys ICV, and provide user support for physical verification debugging.
- Automate and support third-party IP onboarding on physical verification signoff for internal design teams.
- Support tape-out, design-related foundry interface activities, physical verification CAD flows, and CAD flows for SoC integration.
- Develop and maintain validation procedures for physical verification flows, create validation test cases using full custom layout tools, and prepare user guides.
- Automate design tasks, including physical verification flows, design rule decks, and layout migration.
- Integrate EDA tools and optimize design methodologies across digital and analog IC design, verification, and physical implementation.
What you'll need
- Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5+ years of related professional experience (or Master's/PhD with 3+ years).
- Minimum of 5 years of experience in CAD and EDA tool development and support.
- In-depth hands-on experience with tools from Cadence, Synopsys, or Mentor Graphics, along with scripting proficiency in Tcl, Perl, or Python.
- Hands-on experience with Synopsys ICV.
- Understanding of the complete IC design flow, spanning front-end design (RTL, synthesis, simulation) and back-end physical implementation (place and route, timing analysis, physical verification).
Nice to have
- Experience with Mentor Calibre SVRF / TVF.
More semiconductor jobs: Marvell Technology jobs · EDA tools engineer jobs · Santa Clara jobs
First seen in our index 0 days ago, well below the 69-day median for EDA/CAD Engineering roles.
EDA/CAD Engineering · EDA Tools
|
Open roles in category
739
|
Median days since first seen
69 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (739 roles · 78 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 739 |
| Open roles in the wider Physical Implementation family | 26 | 1614 · 117 employers |
| Median days since first seen | 47 d | 69 d (+22 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Who's hiring in this category
- Cadence Design Systems · 162 open roles · median 166 d
- Synopsys · 63 open roles · median 55 d
- Micron Technology · 47 open roles · median 48 d
- NVIDIA · 45 open roles · median 106 d
- Renesas Electronics · 41 open roles · median 19 d
- Keysight Technologies · 34 open roles · median 97 d
How we counted: 739 open EDA/CAD Engineering (EDA Tools) roles from 78 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.