Senior Static Timing Analysis (STA) Engineer (IL)
About the role
Xsight Labs is seeking a Senior Static Timing Analysis (STA) Engineer to join the ASIC implementation team, owning timing analysis, timing closure, and signoff for complex SoC designs at advanced technology nodes.
What you'll do
- Own full-chip and block-level timing closure from synthesis through signoff.
- Perform static timing analysis across multiple operating modes and PVT corners, including SI-aware timing analysis and crosstalk delay/noise debugging.
- Develop, review, and maintain timing constraints (SDC), and validate timing exceptions such as false paths, multicycle paths, asynchronous paths, and generated clocks.
- Analyze and resolve setup, hold, recovery, removal, clock gating, and pulse width violations.
- Collaborate with Physical Design teams to optimize placement, CTS, routing, and generate/validate timing ECOs.
- Develop automation scripts in Tcl and Shell to improve timing analysis, reporting, and signoff correlation.
What you'll need
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum 5 years of experience in ASIC Static Timing Analysis or Physical Design.
- Expertise in advanced technology nodes (such as 16nm, 7nm, 5nm, 3nm) alongside MCMM, SI, OCV, AOCV, POCV, SOCV, and CRPR variation modeling.
- Working knowledge of Liberty (.lib), SPEF, SDF, and Verilog formats.
- Proficiency with EDA tools including Synopsys PrimeTime, Synopsys Fusion, Cadence Innovus, Cadence Tempus, or Synopsys StarRC.
- Strong scripting proficiency in Tcl and Shell within Linux/Unix environments, and familiarity with Git.
Nice to have
- Experience with hierarchical and full-chip timing signoff.
- Experience with timing signoff automation and methodology development.
- Understanding of synthesis, place-and-route, and physical implementation flows.
- Scripting familiarity with Perl or Python.
More semiconductor jobs: Physical design jobs
First seen in our index 6 days ago, well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
713
|
Median days since first seen
62 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Xsight Labs | All employers we track in this specialty (713 roles · 87 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 713 |
| Open roles in the wider Physical Implementation family | 2 | 1619 · 117 employers |
| Median days since first seen | 6 d | 62 d (+56 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Who's hiring in this category
- Qualcomm · 106 open roles · median 61 d
- AMD · 64 open roles · median 42 d
- Broadcom · 46 open roles · median 33 d
- NVIDIA · 46 open roles · median 82 d
- Synopsys · 43 open roles · median 41 d
- Intel Corporation · 31 open roles · median 33 d
How we counted: 713 open Physical Design (Physical Design) roles from 87 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.