Sr Principal Test Engineer - Irvine, CA, United States
Originally posted 16 September 2026 by the employer — open 0 days.
About the role
This role involves providing unique and optimized test solutions as part of the Core Test Technology Group, focusing on advanced technologies including Custom ASIC, Network Switch, and Server & Network Processors.
What you'll do
- Develop product test programs on Advantest 93K tester and Teradyne tester platforms.
- Design tester hardware for high-speed testing.
- Create characterization, production, and wafer sort test programs on the Advantest 93K tester.
- Document detailed test plans and methodologies to meet product specifications.
- Participate in testability reviews with DFT/DFM teams to define and enhance yield and test methodologies.
- Convert test patterns from design simulation environments to ATE format.
- Lead test flow optimization, test time reduction, insertion removals, and yield improvement for production release.
What you'll need
- Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 15-20 years of experience, or a Master's degree with 10-15 years of experience.
- Minimum 10+ years of test program development experience on Advantest 93K ATE tester platform or Teradyne (Uflex or UflexPlus) ATE Tester Platform.
- Experience in ATE testing, test methodology, silicon process, DFT/DFM, and high-speed digital testing.
- 10+ years of experience with C/C++, JAVA, Perl, Python, and Linux environment.
This role has been open 0 days — well below the 26-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
331
|
Median days open
26 d
|
Median salary
$154k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (331 roles · 65 employers) |
|---|---|---|
| Open roles in this specialty | 4 | 331 |
| Open roles in the wider Silicon Validation & Test family | 29 | 1972 · 109 employers |
| Median days open | 4 d | 26 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $154k |
Who's hiring in this category
- Renesas Electronics · 34 open roles · median 26 d
- Infineon Technologies · 32 open roles · median 25 d
- Micron Technology · 22 open roles · median 16 d
- Qualcomm · 21 open roles · median 22 d
- AMD · 17 open roles · median 26 d
- NVIDIA · 16 open roles · median 21 d
How we counted: 331 open Silicon Test Engineering (DFT Test) roles from 65 employers tracked in the SemiconductorJobs index, counted 16 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.