Sr Principal Mixed Signal Verification Engineer - San Jose, CA, United States
$193,100 - $251,100 USD yearly
Originally posted 30 June 2026 by the employer.
About the role
This role leads top-level design verification within the Power Management division, covering motor driver, power-loss protection, point of load, and battery management IC solutions.
What you'll do
- Develop and execute metric-driven design verification plans based upon IC functional, performance, and test specifications. - Develop constrained random tests and automated checkers within the TLDV UVM environment. - Build RNM or VerilogAMS models to support top-level simulation. - Collaborate with the design team to resolve issues identified during verification. - Partner with internal design and test teams to ensure device first-pass testability. - Continuously improve verification methodologies and automate verification tasks where applicable.
What you'll need
- Bachelor’s degree in Electrical Engineering or a related field with focus on mixed-signal circuit design and verification. - 15+ years of experience (or equivalent advanced education and experience) in AMS design or verification of analog and power-management ICs. - Proficiency in UVM environments, including test cases, coverage models, and global checkers. - In-depth knowledge of power-management building blocks such as LDO, Amplifiers, Bandgaps, DCDC regulators, Oscillators, and asynchronous state machines. - Expertise in mixed-signal concepts such as Spice/Spectre and event-based simulator, co-simulation environment, simulation debug, and silicon debug.
Nice to have
- Master’s degree in Electrical Engineering or a related field. - Experience in Top-Down Design Methodology. - Proficiency in shell or Python scripting. - Familiarity with SV-UDN/EENET modeling techniques. - Experience with both GUI and command-line simulation flows. - Proficiency with SV Assertions and Functional coverage. - Understanding integration of AI into a verification workflow.
Skills: UVM, power-management ICs, VerilogAMS, constrained random tests, mixed-signal verification
This role has been open 113 days — well above the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1233
|
Median days open
64 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | QORVO | All employers we track in this specialty (1233 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1233 |
| Open roles in the wider Digital Design & Verification family | 2 | 3283 · 116 employers |
| Median days open | 113 d | 64 d (+49 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, power-management ICs, VerilogAMS, constrained random tests, mixed-signal verification
Who's hiring in this category
- Qualcomm · 115 open roles · median 41 d
- AMD · 93 open roles · median 51 d
- NVIDIA · 84 open roles · median 62 d
- Synopsys · 66 open roles · median 37 d
- SiFive · 55 open roles · median 79 d
- Cadence Design Systems · 51 open roles · median 121 d
How we counted: 1233 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.