PHY Design Verification Engineer - San Diego, United States
Originally posted 21 October 2026 by the employer.
About the role
As a PHY Design Verification Engineer, you will be responsible for pre-silicon RTL verification of wireless PHY and its interfaces with the wireless communication SoC. You will collaborate with DV methodologists, designers, and communication systems engineers to develop reusable testbenches and metric-driven verification environments.
What you'll do
- Execute pre-silicon RTL verification of wireless PHY and its interfaces with the wireless communication SoC. - Develop reusable testbenches and verification environments deploying metric-driven verification methodologies. - Collaborate with DV methodologists, RTL designers, and communication systems engineers to ensure design quality. - Build testbenches, conduct constrained random testing, and drive code and functional coverage closure.
What you'll need
- Bachelor's degree in a relevant technical field. - Advanced knowledge of Verilog, SystemVerilog, UVM, and SystemVerilog Assertions. - Experience with ASIC verification flows, including testbench development, constrained random testing, and code/functional coverage.
Nice to have
- MSEE with 2+ years of verification experience on wireless or wired communication blocks or subsystems. - Experience using Matlab/C reference models and bit-accurate verification. - Knowledge of wireless protocols such as Bluetooth, UWB, WLAN, or Zigbee. - Proficiency in shell, Python, or Perl scripting. - Experience using AI technologies in data mining/analysis. - Experience with Palladium emulation or FPGA validation.
Skills: UVM, SystemVerilog, Verilog, Assertions, Coverage
This role has been open 0 days — well below the 64-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1220
|
Median days open
64 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1220 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 38 | 1220 |
| Open roles in the wider Digital Design & Verification family | 100 | 3283 · 116 employers |
| Median days open | 6 d | 64 d (−58 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: UVM, SystemVerilog, Verilog, Assertions, Coverage
Who's hiring in this category
- Qualcomm · 114 open roles · median 41 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 62 d
- Synopsys · 65 open roles · median 36 d
- SiFive · 55 open roles · median 78 d
- Cadence Design Systems · 50 open roles · median 120 d
How we counted: 1220 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 21 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.